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SINGLE-Ended and Differential S-Parameters
Differential circuits have been important incommunication systems for many years. In the past,differential communication circuits operated at lowfrequencies, where they could be designed andanalyzed using lumped-element models andtechniques. With the frequency of operationincreasing beyond 1GHz, and above 1Gbps fordigital communications, this lumped-elementapproach is no longer valid, because the physicalsize of the circuit approaches the size of awavelength.Distributed models and analysis techniques are nowused instead of lumped-element techniques.Scattering parameters, or S-parameters, have beendeveloped for this purpose [1]. These S-parametersare defined for SINGLE-ended networks. S-parameterscan be used to describe differential networks, but astrict definition was not developed until Bockelmanand others addressed this issue [2]. Bockelman’swork also included a study on how to adapt SINGLE-ended S-parameters for use with differential circuits[2]. This adaptation, called “mixed-mode S-parameters,” addresses differential and common-mode operation, as well as the conversion betweenthe two modes of operation.This application note will explain the use of SINGLE-ended and mixed-mode S-parameters, and the basicconcepts of microwave measurement calibration.
標簽：
差分電路
單端
模式
上傳時間：
2014-03-25
上傳用戶：yyyyyyyyyy
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The NXP LPC314x combine a 270 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, three channel10-bit A/D, and a myriad of serial and parallel interfaces in a SINGLE chip targeted atconsumer, industrial, medical, and communication markets. To optimize system powerconsumption, the LPC314x have multiple power domains and a very flexible ClockGeneration Unit (CGU) that provides dynamic clock gating and scaling.
標簽：
314x
LPC
314
ARM
上傳時間：
2013-10-11
上傳用戶：yuchunhai1990
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The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports SINGLE-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of datamemory, advanced configurable peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals
標簽：
4300
LPC
ARM
雙核微控制器
上傳時間：
2013-10-28
上傳用戶：15501536189
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The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallelinterfaces in a SINGLE chip targeted at consumer, industrial, medical, and communicationmarkets. To optimize system power consumption, the LPC315x have multiple powerdomains and a very flexible Clock Generation Unit (CGU) that provides dynamic clockgating and scaling.The LPC315x is implemented as multi-chip module with two side-by-side dies, one fordigital fuctions and one for analog functions, which include a Power Supply Unit (PSU),audio codec, RTC, and Li-ion battery charger.
標簽：
315x
LPC
315
ARM
上傳時間：
2014-01-17
上傳用戶：Altman
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通過以太網(wǎng)遠程配置Nios II 處理器 應(yīng)用筆記
Firmware in embedded hardware systems is frequently updated over the Ethernet. For
embedded systems that comprise a discrete microprocessor and the devices it controls, the
firmware is the software image run by the microprocessor. When the embedded system
includes an FPGA, firmware updates include updates of the hardware image on the FPGA. If
the FPGA includes a Nios® II soft processor, you can upgrade both the Nios II processor—as
part of the FPGA image—and the software that the Nios II processor runs, in a SINGLE remote
configuration session.
標簽：
Nios
遠程
處理器
應(yīng)用筆記
上傳時間：
2013-11-22
上傳用戶：chaisz
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Nios II定制指令用戶指南：With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Using custom
instructions, you can reduce a complex sequence of standard instructions to a SINGLE instruction implemented in hardware. You can use this feature for a variety of applications, for example, to optimize software inner
loops for digital signal processing (DSP), packet header processing, and computation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphical user interface (GUI) used to add up to 256 custom instructions to the Nios II processor.
The custom instruction logic connects directly to the Nios II arithmetic logic unit (ALU) as shown in Figure 1–1.
標簽：
Nios
定制
指令
用戶
上傳時間：
2013-10-12
上傳用戶：kang1923
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Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective solution. Maxim's 3GPP TS25.104-compliant transceiver solution is presented along withcomplete radio reference designs such as RD2550. For more information on the RD2550, see reference design 5364, "FemtocellRadio Reference Designs Using the MAX2550–MAX2553 Transceivers."
標簽：
Base-Station
Applications
SINGLE-Chip
Transceiver
上傳時間：
2013-11-05
上傳用戶：超凡大師
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This application note covers the design considerations of a system using the performance
features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The
design focuses on high system throughput through the AXI Interconnect core with F
MAX
and
area optimizations in certain portions of the design.
The design uses five AXI video direct memory access (VDMA) engines to simultaneously move
10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p
format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video
test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary
video timing signals. Data read by each AXI VDMA is sent to a common on-screen display
(OSD) core capable of multiplexing or overlaying multiple video streams to a SINGLE output video
stream. The output of the OSD core drives the DVI video display interface on the board.
Performance monitor blocks are added to capture performance data. All 10 video streams
moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are
controlled by a MicroBlaze™ processor.
The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the
Xilinx® ML605 Rev D evaluation board
標簽：
XAPP
740
AXI
互聯(lián)
上傳時間：
2013-11-23
上傳用戶：shen_dafa
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The Xilinx Zynq-7000 Extensible Processing Platform (EPP) redefines the possibilities for embedded systems, giving system and software architects and developers a flexible platform to launch their new solutions and traditional ASIC and ASSP users an alternative that aligns with today’s programmable imperative. The new class of product elegantly combines an industrystandard ARMprocessor-based system with Xilinx 28nm programmable logic—in a SINGLE device. The processor boots first, prior to configuration of the programmable logic. This, along with a streamlined workflow, saves time and effort and lets software developers and hardware designers start development simultaneously.
標簽：
xilinx
Zynq
7000
EPP
上傳時間：
2013-10-09
上傳用戶：evil
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在集成電路內(nèi)建自測試的過程中，電路的測試功耗通常顯著高于正常模式產(chǎn)生的功耗，因此低功耗內(nèi)建自測試技術(shù)已成為當前的一個研究熱點。為了減少被測電路內(nèi)部節(jié)點的開關(guān)翻轉(zhuǎn)活動率，研究了一種隨機單輸入跳變（Random SINGLE Input Change，RSIC）測試向量生成器的設(shè)計方案，利用VHDL語言描述了內(nèi)建自測試結(jié)構(gòu)中的測試向量生成模塊，進行了計算機模擬仿真并用FPGA（EP1C6Q240C8）加以硬件實現(xiàn)。實驗結(jié)果證實了這種內(nèi)建自測試原理電路的正確性和有效性。
標簽：
低功耗測試
矢量
生成技術(shù)
上傳時間：
2013-10-08
上傳用戶：llwap
