<button id="444w4"></button> The PCA9541 is a 2-to-1 I2C-bus master selector designed for high reliability dual masterI2C-bus applications where system operation is required, even when one master fails orthe controller card is removed for maintenance. The two masters (for example, primaryand back-up) are located on separate I2C-buses that connect to the same downstreamI2C-bus SLave devices. I2C-bus commands are sent by either I2C-bus master and are usedto select one master at a time. Either master at any time can gain control of the SLavedevices if the other master is disabled or removed from the system. The failed master isisolated from the system and will not affect communication between the on-line masterand the SLave devices on the downstream I2C-bus.
標(biāo)簽： master C-bus 9541 PCA
上傳時(shí)間： 2013-10-09
上傳用戶：3294322651
The C500 microcontroller family usually provides only one on-chip synchronous serialchannel (SSC). If a second SSC is required, an emulation of the missing interface mayhelp to avoid an external hardware solution with additional electronic components.The solution presented in this paper and in the attached source files emulates the mostimportant SSC functions by using optimized SW routines with a performance up to 25KBaud in SLave Mode with half duplex transmission and an overhead less than 60% atSAB C513 with 12 MHz. Due to the implementation in C this performance is not the limitof the chip. A pure implementation in assembler will result in a strong reduction of theCPU load and therefore increase the maximum speed of the interface. In addition,microcontrollers like the SAB C505 will speed up the interface by a factor of two becauseof an optimized architecture compared with the SAB C513.Moreover, this solution lays stress on using as few on-chip hardware resources aspossible. A more excessive consumption of those resources will result in a highermaximum speed of the emulated interface.Due to the restricted performance of an 8 bit microcontroller a pin compatible solution isprovided only; the internal register based programming interface is replaced by a set ofsubroutine calls.The attached source files also contain a test shell, which demonstrates how to exchangeinformation between an on-chip HW-SSC and the emulated SW-SSC via 5 external wiresin different operation modes. It is based on the SAB C513 (Siemens 8 bit microcontroller).A table with load measurements is presented to give an indication for the fraction of CPUperformance required by software for emulating the SSC.
標(biāo)簽： synchronous Emulating serial
上傳時(shí)間： 2014-01-31
上傳用戶：z1191176801
This application note shows how to write an Inter Integrated Circuit bus driver (I²C) for the Philips P90CL301micro-controller.It is not only an example of writing a driver, but it also includes a set of application interface software routines toquickly implement a complete I²C multi-master system application.For specific applications the user will have to make minimal changes in the driver program. Using the drivermeans linking modules to your application software and including a header-file into the application sourceprograms. A small example program of how to use the driver is listed.The driver supports i.a. polled or interrupt driven message handling, SLave message transfers and multi-mastersystem applications. Furthermore, it is made suitable for use in conjunction with real time operating systems, likepSOS+.
標(biāo)簽： routines driver P90 301
上傳時(shí)間： 2013-11-23
上傳用戶：weixiao99
Presents short and simple I2C software routines that support onlySLave (rather than master or master & SLave) operation and an ASMdemonstration program. The SLave-only software in this app notecomplements the master mode software presented in AN464, Usingthe 87LPC76X microcontroller as an I2C bus master.
上傳時(shí)間： 2013-11-22
上傳用戶：1039312764
I2C interface, is a very powerful tool for system designers. Theintegrated protocols allow systems to be completely software defined.Software development time of different products can be reduced byassembling a library of reusable software modules. In addition, themultimaster capability allows rapid testing and alignment ofend-products via external connections to an assembly-line computer.The mask programmable 87LPC76X and its EPROM version, the87LPC76X, can operate as a master or a SLave device on the I2Csmall area network. In addition to the efficient interface to thededicated function ICs in the I2C family, the on-board interfacefacilities I/O and RAM expansion, access to EEPROM andprocessor-to-processor communications.
標(biāo)簽： microcontro Using 76X LPC
上傳時(shí)間： 2013-12-30
上傳用戶：Artemis
基于多點(diǎn)網(wǎng)絡(luò)的水廠自動(dòng)監(jiān)控系統(tǒng)設(shè)計(jì)Design of MPI Based Automatic Monitoring and Control System in Water Works劉 美 俊(湖南工程學(xué)院，湘潭411101)摘要針對水廠工作水泵多、現(xiàn)場離控制站距離遠(yuǎn)的特點(diǎn)，提出了一種基于MPI多點(diǎn)網(wǎng)絡(luò)的自動(dòng)監(jiān)控系統(tǒng)的設(shè)計(jì)方法，分析了系統(tǒng)的工作原理，介紹了系統(tǒng)中數(shù)據(jù)的采集與處理、主站與從站的通信原理以及系統(tǒng)軟件的設(shè)計(jì)。由于這種系統(tǒng)的主、從站PLC之間采用MPI網(wǎng)絡(luò)通信，具有運(yùn)行可靠、性能價(jià)格比高的特點(diǎn)，所以適用于中小規(guī)模水廠的分布式監(jiān)控場合。關(guān)鍵詞多點(diǎn)網(wǎng)絡(luò)主站從站監(jiān)控系統(tǒng)Abstract Ina ccordancew ithth efe atuersof w aterw orks,i. e. ，manyp umpsin o perationa ndth ep umps， farfor mt hec ontrolst ation,th em ethodo fdesigninga na utomati(〕monitoringa ndc ontorlsy stemb asedo nM PIis p resented.Th eo perationalpr incipleo fth esy stemi san alyzed,th ed atac olection,data processing; communication between master station and SLave station as wel as design and system software are discussed. Because MPI network communicationis used among master station, SLave stations and PLC, the system is reliable and high cost-efective. It is， suitable for smal and mediumsized water works for distrbuted monitoring and control.Keywords MPI Masterst ation SLaves tation Monitoringa ndc ontorlsy stem 自來 水 廠 的自動(dòng)控制系統(tǒng)一般分為兩大部分，一對組態(tài)硬件要求較高，投資較大。相對而言，MPI網(wǎng)是水源地深水泵的工作控制，一是水廠區(qū)變頻恒壓供絡(luò)速度可達(dá)187.5 M bps，通過一級(jí)中繼器傳輸距離可水控制，兩部分的實(shí)際距離通常都比較遠(yuǎn)。某廠水源達(dá)Ikm 。根據(jù)水廠的具體情況，確定以MPI方式組地有3臺(tái)深井泵給水廠區(qū)的蓄水池供水。水廠區(qū)的成網(wǎng)絡(luò)，主站PLC為S7-300系列的CPU3121FM，從任務(wù)是對水池的水進(jìn)行消毒處理后，通過加壓泵向管站為S7-200系列的CPU222。這樣既滿足了系統(tǒng)要路恒壓供水。選用Siemens公司的S7系列可編程控求，又相對于Profibus網(wǎng)絡(luò)節(jié)省了三分之一的成本，制器(PLC)和上位機(jī)組成實(shí)時(shí)數(shù)據(jù)采集和監(jiān)控系統(tǒng)， 這種分布式監(jiān)控系統(tǒng)具有較高的性能價(jià)格比。系統(tǒng)對深水泵進(jìn)行遠(yuǎn)程控制，對供水泵采用變頻器進(jìn)行恒中PLC的物理層采用RS - 485接口，網(wǎng)絡(luò)延伸選用壓控制以保證整個(gè)水廠的電機(jī)設(shè)備安全、可靠地運(yùn)帶防雷保護(hù)的中繼器，使系統(tǒng)的安全運(yùn)行得到了保行。證。MPI網(wǎng)絡(luò)的拓?fù)浣Y(jié)構(gòu)如圖1所示。1 多點(diǎn)網(wǎng)絡(luò)(NWI)監(jiān)控系統(tǒng)的組成Sie me ns 公司S7系列PLC通常有MP」多點(diǎn)網(wǎng)絡(luò)與Profibus現(xiàn)場總線網(wǎng)絡(luò)兩種組網(wǎng)方式。Profibus現(xiàn)場總線的應(yīng)用目前較為普遍，通用性較好，它由Profibus一DP, Profibus一FMS, Profibus一PA組成。Profibus - DP型用于分散外設(shè)間的數(shù)據(jù)傳輸，傳輸速率為9.6kbps一12Mbps，主要用于現(xiàn)場控制器與分散1/0之間的通信，可滿足交直流調(diào)速系統(tǒng)快速響應(yīng)的時(shí)間要求，特別適合于加工自動(dòng)化領(lǐng)域的應(yīng)用;Profibus - FMS主要解決車間級(jí)通信問題，完成中等傳輸速度的循環(huán)或非循環(huán)數(shù)據(jù)交換任務(wù)，適用于紡織、樓宇自動(dòng)化、可編程控制器、低壓開關(guān)等;Profibus - PA型采用了OSI模型的物理層和數(shù)據(jù)鏈路層，適用于過程自動(dòng)化的總線類型。
標(biāo)簽： 多點(diǎn) 網(wǎng)絡(luò) 系統(tǒng)設(shè)計(jì) 自動(dòng)監(jiān)控
上傳時(shí)間： 2013-10-09
上傳用戶：fac1003
Abstract: Designers who must interface 1-Wire temperature sensors with Xilinx field-programmable gate arrays(FPGAs) can use this reference design to drive a DS28EA00 1-Wire SLave device. The downloadable softwarementioned in this document can also be used as a starting point to connect other 1-Wire SLave devices. The systemimplements a 1-Wire master connected to a UART and outputs temperature to a PC from the DS28EA00 temperaturesensor. In addition, high/low alarm outputs are displayed from the DS28EA00 PIO pins using LEDs.
標(biāo)簽： PicoBlaze Create Master Xilinx
上傳時(shí)間： 2013-11-05
上傳用戶：a6697238
Abstract: Communication with 1-Wire SLave devices requires a 1-Wire master. There are numerous ways to build a 1-Wire master (see reference design 4206, "Choosing the Right 1-Wire Master for Embedded Applications"). Thisdocument describes the DS1WM, a synthesizable 1-Wire master that can be implemented in an application-specificintegrated circuit (ASIC) or field-programmable gate array (FPGA).
上傳時(shí)間： 2014-12-22
上傳用戶：xanxuan
ZigBee技術(shù)是一種應(yīng)用于短距離范圍內(nèi)，低傳輸數(shù)據(jù)速率下的各種電子設(shè)備之間的無線通信技術(shù)。ZigBee名字來源于蜂群使用的賴以生存和發(fā)展的通信方式，蜜蜂通過跳ZigZag形狀的舞蹈來通知發(fā)現(xiàn)的新食物源的位置、距離和方向等信息，以此作為新一代無線通訊技術(shù)的名稱。ZigBee過去又稱為“HomeRF Lite”、“RF-EasyLink”或“FireFly”無線電技術(shù)，目前統(tǒng)一稱為ZigBee技術(shù)。 2、ZigBee技術(shù)的特點(diǎn) 自從馬可尼發(fā)明無線電以來，無線通信技術(shù)一直向著不斷提高數(shù)據(jù)速率和傳輸距離的方向發(fā)展。例如：廣域網(wǎng)范圍內(nèi)的第三代移動(dòng)通信網(wǎng)絡(luò)（3G）目的在于提供多媒體無線服務(wù)，局域網(wǎng)范圍內(nèi)的標(biāo)準(zhǔn)從IEEE802.11的1Mbit/s到IEEE802.11g的54Mbit/s的數(shù)據(jù)速率。而當(dāng)前得到廣泛研究的ZigBee技術(shù)則致力于提供一種廉價(jià)的固定、便攜或者移動(dòng)設(shè)備使用的極低復(fù)雜度、成本和功耗的低速率無線通信技術(shù)。這種無線通信技術(shù)具有如下特點(diǎn)： 功耗低：工作模式情況下，ZigBee技術(shù)傳輸速率低，傳輸數(shù)據(jù)量很小，因此信號(hào)的收發(fā)時(shí)間很短，其次在非工作模式時(shí)，ZigBee節(jié)點(diǎn)處于休眠模式。設(shè)備搜索時(shí)延一般為30ms，休眠激活時(shí)延為15ms，活動(dòng)設(shè)備信道接入時(shí)延為15ms。由于工作時(shí)間較短、收發(fā)信息功耗較低且采用了休眠模式，使得ZigBee節(jié)點(diǎn)非常省電，ZigBee節(jié)點(diǎn)的電池工作時(shí)間可以長達(dá)6個(gè)月到2年左右。同時(shí)，由于電池時(shí)間取決于很多因素，例如：電池種類、容量和應(yīng)用場合，ZigBee技術(shù)在協(xié)議上對電池使用也作了優(yōu)化。對于典型應(yīng)用，堿性電池可以使用數(shù)年，對于某些工作時(shí)間和總時(shí)間（工作時(shí)間+休眠時(shí)間）之比小于1%的情況，電池的壽命甚至可以超過10年。 數(shù)據(jù)傳輸可靠：ZigBee的媒體接入控制層（MAC層）采用talk-when-ready的碰撞避免機(jī)制。在這種完全確認(rèn)的數(shù)據(jù)傳輸機(jī)制下，當(dāng)有數(shù)據(jù)傳送需求時(shí)則立刻傳送，發(fā)送的每個(gè)數(shù)據(jù)包都必須等待接收方的確認(rèn)信息，并進(jìn)行確認(rèn)信息回復(fù)，若沒有得到確認(rèn)信息的回復(fù)就表示發(fā)生了碰撞，將再傳一次，采用這種方法可以提高系統(tǒng)信息傳輸?shù)目煽啃浴Ｍ瑫r(shí)為需要固定帶寬的通信業(yè)務(wù)預(yù)留了專用時(shí)隙，避免了發(fā)送數(shù)據(jù)時(shí)的競爭和沖突。同時(shí)ZigBee針對時(shí)延敏感的應(yīng)用做了優(yōu)化，通信時(shí)延和休眠狀態(tài)激活的時(shí)延都非常短。 網(wǎng)絡(luò)容量大：ZigBee低速率、低功耗和短距離傳輸?shù)奶攸c(diǎn)使它非常適宜支持簡單器件。ZigBee定義了兩種器件：全功能器件（FFD）和簡化功能器件（RFD）。對全功能器件，要求它支持所有的49個(gè)基本參數(shù)。而對簡化功能器件，在最小配置時(shí)只要求它支持38個(gè)基本參數(shù)。一個(gè)全功能器件可以與簡化功能器件和其他全功能器件通話，可以按3種方式工作，分別為：個(gè)域網(wǎng)協(xié)調(diào)器、協(xié)調(diào)器或器件。而簡化功能器件只能與全功能器件通話，僅用于非常簡單的應(yīng)用。一個(gè)ZigBee的網(wǎng)絡(luò)最多包括有255個(gè)ZigBee網(wǎng)路節(jié)點(diǎn)，其中一個(gè)是主控（Master）設(shè)備，其余則是從屬（SLave）設(shè)備。若是通過網(wǎng)絡(luò)協(xié)調(diào)器（Network Coordinator），整個(gè)網(wǎng)絡(luò)最多可以支持超過64000個(gè)ZigBee網(wǎng)路節(jié)點(diǎn)，再加上各個(gè)Network Coordinator可互相連接，整個(gè)ZigBee網(wǎng)絡(luò)節(jié)點(diǎn)的數(shù)目將十分可觀。 兼容性：ZigBee技術(shù)與現(xiàn)有的控制網(wǎng)絡(luò)標(biāo)準(zhǔn)無縫集成。通過網(wǎng)絡(luò)協(xié)調(diào)器（Coordinator）自動(dòng)建立網(wǎng)絡(luò)，采用載波偵聽/沖突檢測（CSMA-CA）方式進(jìn)行信道接入。為了可靠傳遞，還提供全握手協(xié)議。
標(biāo)簽： zigbee
上傳時(shí)間： 2013-11-24
上傳用戶：siguazgb
3 FPGA設(shè)計(jì)流程 完整的FPGA 設(shè)計(jì)流程包括邏輯電路設(shè)計(jì)輸入、功能仿真、綜合及時(shí)序分析、實(shí)現(xiàn)、加載配置、調(diào)試。FPGA 配置就是將特定的應(yīng)用程序設(shè)計(jì)按FPGA設(shè)計(jì)流程轉(zhuǎn)化為數(shù)據(jù)位流加載到FPGA 的內(nèi)部存儲(chǔ)器中，實(shí)現(xiàn)特定邏輯功能的過程。由于FPGA 電路的內(nèi)部存儲(chǔ)器都是基于RAM 工藝的，所以當(dāng)FPGA電路電源掉電后，內(nèi)部存儲(chǔ)器中已加載的位流數(shù)據(jù)將隨之丟失。所以，通常將設(shè)計(jì)完成的FPGA 位流數(shù)據(jù)存于外部存儲(chǔ)器中，每次上電自動(dòng)進(jìn)行FPGA電路配置加載。 4 FPGA配置原理 以Xilinx公司的Qpro Virtex Hi-Rel系列XQV100電路為例，F(xiàn)PGA的配置模式有四種方案可選擇：MasterSerial Mode，SLave Serial Mode，Master selectMAPMode，SLave selectMAP Mode。配置是通過芯片上的一組專/ 復(fù)用引腳信號(hào)完成的，主要配置功能信號(hào)如下： (1)M0、M1、M2：下載配置模式選擇; (2)CLK：配置時(shí)鐘信號(hào); (3)DONE：顯示配置狀態(tài)、控制器件啟動(dòng);
標(biāo)簽： Xilinx FPGA 集成電路 動(dòng)態(tài)老化
上傳時(shí)間： 2013-11-18
上傳用戶：oojj
蟲蟲下載站版權(quán)所有 京ICP備2021023401號(hào)-1
<button id="44ciy"></button>