-
This white paper discusses how market trends, the need for increased productivity, and new legislation have
accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is
changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to
market. This allows FPGA users to design their own customized safety controllers and provides a significant
competitive advantage over traditional microcontroller or ASIC-based designs.
Introduction
The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in
cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas
around machines such as fast-moving robots, and distributed control systems in process automation equipment such
as those used in petrochemical plants.
The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of
electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing
safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was
developed in the mid-1980s and has been revised several times to cover the technical advances in various industries.
In addition, derivative standards have been developed for specific markets and applications that prescribe the
particular requirements on functional safety systems in these industry applications. Example applications include
process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC
62304), automotive (ISO 26262), power generation, distribution, and transportation.
圖Figure 1. Local Safety System
標簽：
FPGA
安全系統
上傳時間：
2013-11-05
上傳用戶：維子哥哥
-
The PLB BRAM Interface Controller is a module thatattaches to the PLB (Processor Local Bus).
標簽：
Block
BRAM
PLB
RAM
上傳時間：
2013-10-27
上傳用戶：zoudejile
-
很多不同的廠家生產各種型號的計算機，它們運行完全不同的操作系統，但TCP.IP協議族允許它們互相進行通信。這一點很讓人感到吃驚，因為它的作用已遠遠超出了起初的設想。T C P / I P起源于6 0年代末美國政府資助的一個分組交換網絡研究項目，到9 0年代已發展成為計算機之間最常應用的組網形式。它是一個真正的開放系統，因為協議族的定義及其多種實現可以不用花錢或花很少的錢就可以公開地得到。它成為被稱作“全球互聯網”或“因特網(Internet)”的基礎，該廣域網（WA N）已包含超過1 0 0萬臺遍布世界各地的計算機。本章主要對T C P / I P協議族進行概述，其目的是為本書其余章節提供充分的背景知識。
TCP.IP協議 縮略語
ACK (ACKnowledgment) TCP首部中的確認標志
API (Application Programming Interface) 應用編程接口
ARP (Address Resolution Protocol) 地址解析協議
ARPANET(Defense Advanced Research Project Agency NETwork) (美國)國防部遠景研究規劃局
AS (Autonomous System) 自治系統
ASCII (American Standard Code for Information Interchange) 美國信息交換標準碼
ASN.1 (Abstract Syntax Notation One) 抽象語法記法1
BER (Basic Encoding Rule) 基本編碼規則
BGP (Border Gateway Protocol) 邊界網關協議
BIND (Berkeley Internet Name Domain) 伯克利I n t e r n e t域名
BOOTP (BOOTstrap Protocol) 引導程序協議
BPF (BSD Packet Filter) BSD 分組過濾器
CIDR (Classless InterDomain Routing) 無類型域間選路
CIX (Commercial Internet Exchange) 商業互聯網交換
CLNP (ConnectionLess Network Protocol) 無連接網絡協議
CRC (Cyclic Redundancy Check) 循環冗余檢驗
CSLIP (Compressed SLIP) 壓縮的S L I P
CSMA (Carrier Sense Multiple Access) 載波偵聽多路存取
DCE (Data Circuit-terminating Equipment) 數據電路端接設備
DDN (Defense Data Network) 國防數據網
DF (Don’t Fragment) IP首部中的不分片標志
DHCP (Dynamic Host Configuration Protocol) 動態主機配置協議
DLPI (Data Link Provider Interface) 數據鏈路提供者接口
DNS (Domain Name System) 域名系統
DSAP (Destination Service Access Point) 目的服務訪問點
DSLAM (DSL Access Multiplexer) 數字用戶線接入復用器
DSSS (Direct Sequence Spread Spectrum) 直接序列擴頻
DTS (Distributed Time Service) 分布式時間服務
DVMRP (Distance Vector Multicast Routing Protocol) 距離向量多播選路協議
EBONE (European IP BackbONE) 歐洲I P主干網
EOL (End of Option List) 選項清單結束
EGP (External Gateway Protocol) 外部網關協議
EIA (Electronic Industries Association) 美國電子工業協會
FCS (Frame Check Sequence) 幀檢驗序列
FDDI (Fiber Distributed Data Interface) 光纖分布式數據接口
FIFO (First In, First Out) 先進先出
FIN (FINish) TCP首部中的結束標志
FQDN (Full Qualified Domain Name) 完全合格的域名
FTP (File Transfer Protocol) 文件傳送協議
HDLC (High-level Data Link Control) 高級數據鏈路控制
HELLO 選路協議
IAB (Internet Architecture Board) Internet體系結構委員會
IANA (Internet Assigned Numbers Authority) Internet號分配機構
ICMP (Internet Control Message Protocol) Internet控制報文協議
IDRP (InterDomain Routing Protocol) 域間選路協議
IEEE (Institute of Electrical and Electronics Engineering) （美國）電氣與電子工程師協會
IEN (Internet Experiment Notes) 互聯網試驗注釋
IESG (Internet Engineering Steering Group) Internet工程指導小組
IETF (Internet Engineering Task Force) Internet工程專門小組
IGMP (Internet Group Management Protocol) Internet組管理協議
IGP (Interior Gateway Protocol) 內部網關協議
IMAP (Internet Message Access Protocol) Internet報文存取協議
IP (Internet Protocol) 網際協議
I RTF (Internet Research Task Force) Internet研究專門小組
IS-IS (Intermediate System to Intermediate System Protocol) 中間系統到中間系統協議
ISN (Initial Sequence Number) 初始序號
ISO (International Organization for Standardization) 國際標準化組織
ISOC (Internet SOCiety) Internet協會
LAN (Local Area Network) 局域網
LBX (Low Bandwidth X) 低帶寬X
LCP (Link Control Protocol) 鏈路控制協議
LFN (Long Fat Net) 長肥網絡
LIFO (Last In, First Out) 后進先出
LLC (Logical Link Control) 邏輯鏈路控制
LSRR (Loose Source and Record Route) 寬松的源站及記錄路由
MBONE (Multicast Backbone On the InterNEt) Internet上的多播主干網
MIB (Management Information Base) 管理信息庫
MILNET (MILitary NETwork) 軍用網
MIME (Multipurpose Internet Mail Extensions) 通用I n t e r n e t郵件擴充
MSL (Maximum Segment Lifetime) 報文段最大生存時間
MSS (Maximum Segment Size) 最大報文段長度
M TA (Message Transfer Agent) 報文傳送代理
MTU (Maximum Transmission Unit) 最大傳輸單元
NCP (Network Control Protocol) 網絡控制協議
NFS (Network File System) 網絡文件系統
NIC (Network Information Center) 網絡信息中心
NIT (Network Interface Tap) 網絡接口栓（S u n公司的一個程序）
NNTP (Network News Transfer Protocol) 網絡新聞傳送協議
NOAO (National Optical Astronomy Observatories) 國家光學天文臺
NOP (No Operation) 無操作
NSFNET (National Science Foundation NETwork) 國家科學基金網絡
NSI (NASA Science Internet) （美國）國家宇航局I n t e r n e t
NTP (Network Time Protocol) 網絡時間協議
NVT (Network Virtual Terminal) 網絡虛擬終端
OSF (Open Software Foudation) 開放軟件基金
OSI (Open Systems Interconnection) 開放系統互連
OSPF (Open Shortest Path First) 開放最短通路優先
PAWS (Protection Against Wrapped Sequence number) 防止回繞的序號
PDU (Protocol Data Unit) 協議數據單元
POSIX (Portable Operating System Interface) 可移植操作系統接口
PPP (Point-to-Point Protocol) 點對點協議
PSH (PuSH) TCP首部中的急迫標志
RARP (Reverse Address Resolution Protocol) 逆地址解析協議
RFC (Request For Comments) Internet的文檔，其中的少部分成為標準文檔
RIP (Routing Information Protocol) 路由信息協議
RPC (Remote Procedure Call) 遠程過程調用
RR (Resource Record) 資源記錄
RST (ReSeT) TCP首部中的復位標志
RTO (Retransmission Time Out) 重傳超時
RTT (Round-Trip Time) 往返時間
SACK (Selective ACKnowledgment) 有選擇的確認
SLIP (Serial Line Internet Protocol) 串行線路I n t e r n e t協議
SMI (Structure of Management Information) 管理信息結構
SMTP (Simple Mail Transfer Protocol) 簡單郵件傳送協議
SNMP (Simple Network Management Protocol) 簡單網絡管理協議
SSAP (Source Service Access Point) 源服務訪問點
SSRR (Strict Source and Record Route) 嚴格的源站及記錄路由
SWS (Silly Window Syndrome) 糊涂窗口綜合癥
SYN (SYNchronous) TCP首部中的同步序號標志
TCP (Transmission Control Protocol) 傳輸控制協議
TFTP (Trivial File Transfer Protocol) 簡單文件傳送協議
TLI (Transport Layer Interface) 運輸層接口
TTL (Ti m e - To-Live) 生存時間或壽命
TUBA (TCP and UDP with Bigger Addresses) 具有更長地址的T C P和U D P
Telnet 遠程終端協議
UA (User Agent) 用戶代理
UDP (User Datagram Protocol) 用戶數據報協議
URG (URGent) TCP首部中的緊急指針標志
UTC (Coordinated Universal Time) 協調的統一時間
UUCP (Unix-to-Unix CoPy) Unix到U n i x的復制
WAN (Wide Area Network) 廣域網
WWW (World Wide Web) 萬維網
XDR (eXternal Data Representation) 外部數據表示
XID (transaction ID) 事務標識符
XTI (X/Open Transport Layer Interface) X/ O p e n運輸層接口
標簽：
tcp
協議
上傳時間：
2013-11-13
上傳用戶：tdyoung
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VLAN(Virtual Local Area Network)的中文名為"虛擬局域網"。VLAN是一種將局域網設備從邏輯上劃分成一個個網段，從而實現虛擬工作組的新興數據交換技術。這一新興技術主要應用于交換機和路由器中，但主流應用還是在交換機之中。
標簽：
VLAN
上傳時間：
2013-11-19
上傳用戶：comua
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支持的平臺本節列出了 RealView™ ARMulator® ISS v1.3 在以下環境中運行所必須要符合的硬件要求和軟件要求• Microsoft Windows• SPARC 工作站• Linux浮動許可證管理要求安裝配置 TCP/IP 軟件并在每臺相關的計算機中運行有關使用 FLEXlm 許可證管理軟件安裝許可證的詳細信息請參閱 ARM FLEXlm License Management Guide注釋要查看 PDF 版本的手冊您必須安裝 Adobe Acrobat ™ RealView ARMulator ISS v1.3 CD-ROM 上有Acrobat Reader 如果尚未安裝可以單獨進行安裝Windows 和 Solaris 系統中還有以 DynaText 格式查看的在線手冊在這些系統中安裝 RealViewARMulator ISS v1.3 時也會安裝 DynaText 查看器
標簽：
RealView
Debugger
用戶手冊
上傳時間：
2013-11-08
上傳用戶：manlian
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The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embeddedapplications. The ARM Cortex-M3 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC1850/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals. The ARMCortex-M3 CPU also includes an internal prefetch unit that supports speculativebranching.The LPC1850/30/20/10 include up to 200 kB of on-chip SRAM data memory, a quad SPIFlash Interface (SPIFI), a State Configuration Timer (SCT) subsystem, two High-speedUSB controllers, Ethernet, LCD, an external memory controller, and multiple digital andanalog peripherals.
標簽：
Cortex-M
1850
LPC
內核微控制器
上傳時間：
2014-12-31
上傳用戶：zhuoying119
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The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of datamemory, advanced configurable peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals
標簽：
4300
LPC
ARM
雙核微控制器
上傳時間：
2013-10-28
上傳用戶：15501536189
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This white paper discusses how market trends, the need for increased productivity, and new legislation have
accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is
changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to
market. This allows FPGA users to design their own customized safety controllers and provides a significant
competitive advantage over traditional microcontroller or ASIC-based designs.
Introduction
The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in
cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas
around machines such as fast-moving robots, and distributed control systems in process automation equipment such
as those used in petrochemical plants.
The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of
electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing
safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was
developed in the mid-1980s and has been revised several times to cover the technical advances in various industries.
In addition, derivative standards have been developed for specific markets and applications that prescribe the
particular requirements on functional safety systems in these industry applications. Example applications include
process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC
62304), automotive (ISO 26262), power generation, distribution, and transportation.
圖Figure 1. Local Safety System
標簽：
FPGA
安全系統
上傳時間：
2013-11-14
上傳用戶：zoudejile
-
The PLB BRAM Interface Controller is a module thatattaches to the PLB (Processor Local Bus).
標簽：
Block
BRAM
PLB
RAM
上傳時間：
2013-10-27
上傳用戶：Breathe0125
-
The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Specification Revision 2.0a ([Ref 6]) dictates that when a target signals adata transfer, "the target must do so within 16 clocks of the assertion of FRAME#." PCItermination transactions, such as Split Response/Complete, are commonly used to meet thelatency specifications. This method adds complexity to the design, as well as additional systemlatency. Another solution is to increase the ratio of the memory frequency to the PCI-X busfrequency. However, this solution increases the required power and clock resource usage.
標簽：
PCI-X
XAPP
DIMM
708
上傳時間：
2013-11-24
上傳用戶：18707733937
