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This document gives the code for programming a CC2500 transceiver using Altera Stratix FPGA. The FPGA and CC2500 are connected through SPI mode with the FPGA as the master and CC2500 as the slave.
標簽： programming transceiver document Stratix
上傳時間： 2014-01-15
上傳用戶：wuyuying
本函數在matlab實現阻抗圓圖，通過調用switch（）函數，可以得出傳輸線的反射系數，以及支節匹配等參數，本函數可以實現單、雙和三支節匹配。
上傳時間： 2014-01-06
上傳用戶：jennyzai
This program requires the DSP2833x header files. // // This program requires an external I2C RTC connected to // the I2C bus at address 0x6f. // // As supplied, this project is configured for "boot to SARAM" // operation. The 2833x Boot Mode table is shown below. // For information on configuring the boot mode of an eZdsp, // please refer to the documentation included with the eZdsp,
標簽： requires program This external
上傳時間： 2017-07-12
上傳用戶：dianxin61
This program requires the DSP2833x header files. // // As supplied, this project is configured for "boot to SARAM" // operation. The 2833x Boot Mode table is shown below. // For information on configuring the boot mode of an eZdsp, // please refer to the documentation included with the eZdsp,
標簽： configured requires supplied program
上傳時間： 2014-01-10
上傳用戶：lixinxiang
此題目是通過鍵盤來實現密碼輸入是否正確，正確的時候數碼管亮，否則發出報警聲。 判斷是按鍵還是干擾是非常有用的，它體現了一個系統的抗干擾能力。高低電平在瞬間的變換是很正常的，如果沒有這條語句，系統很容易出錯。 其中2秒是由定時器0來完成的。 在程序的定時器中斷中，用switch代替了if else結構，使得程序的可讀性大大增強。 TH0 = (65536-50000) / 256 TL0 = (65536-50000) 256 使得TH0 = 3CH, TL0 = B0H,由于該單片機的晶振為12MHz 因此定時時間就為0.05ms.在定時器中斷服務程序中用FLASH計數，當計數達到40時正好是2秒。
上傳時間： 2014-01-21
上傳用戶：caozhizhi
This software is developed to provide ease with controller design. For PID control, options are given to design and analyse the compensated and uncompensated system. You are free to choice among Proportional PI, PD and PID mode of control. Both frequency and time domain characteristics can be observed. Special Menus are given to observe time and frequency response plots. For Statefeedback controller similar options are given. But this is limited to second order system only.
標簽： controller developed software control
上傳時間： 2017-07-25
上傳用戶：aysyzxzm
RS_latch using vhdl, When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR (Not OR) logic gates. The stored bit is present on the output marked Q. Normally, in storage mode, the S and R inputs are both low, and feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If S (Set) is pulsed high while R is held low, then the Q output is forced high, and stays high when S returns to low similarly, if R (Reset) is pulsed high while S is held low, then the Q output is forced low, and stays low when R returns to low.
標簽： using fundamental the RS_latch
上傳時間： 2017-07-30
上傳用戶：努力努力再努力
hese are the zip files that are associated with application note ADSP-BF533 Blackfin Booting Process (EE-240) example.zip: Used throughout the EE-note to explain in detail the various booting modes. BF533 Ez Kit Multiple DXE Boot.zip: Multi-DXE Boot Example used with the ADSP-BF533 Ez-Kit Lite. Host Boot.zip: Example Host code to demonstrate SPI Slave Mode Booting Program_Atmel.zip: Example code that programs the Atmel DataFlashes via an ADSP-BF532 Processor All programs have been written for VisualDSP++ 3.5
標簽： application associated are Blackfin
上傳時間： 2017-07-30
上傳用戶：tonyshao
矩陣鍵盤程序，主要教會初學者練習switch語句，同時練習條件語句，用于鍵盤掃描
標簽： 矩陣鍵盤程序
上傳時間： 2014-01-24
上傳用戶：wanqunsheng
視頻質料 在matlab環境中如何使用radiobutton，switch語句，邊緣檢測
標簽： radiobutton matlab 視頻 環境
上傳時間： 2017-08-15
上傳用戶：thesk123
