The GRLIB IP Library is an integrated set of reusable IP cores, designed for SYstem-on-chip (SOC) development. The IP cores are centered around the common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources.
標(biāo)簽： SYstem-on-chip integrated designed reusable
上傳時(shí)間： 2013-12-20
上傳用戶：小眼睛LSL
ARM SYstem-on-chip Architecture經(jīng)典之書。學(xué)習(xí)ARM架構(gòu)的好書。
標(biāo)簽： SYstem-on-chip Architecture ARM
上傳時(shí)間： 2014-01-17
上傳用戶：gxmm
TI DaVinci EVM 基于達(dá)芬奇技術(shù)的TMS320DM6446 Digital Media SYstem-on-chip的Bootloader源代碼！
標(biāo)簽： SYstem-on-chip Bootloader DaVinci Digital
上傳時(shí)間： 2015-08-26
上傳用戶：jeffery
The GRLIB IP Library is an integrated set of reusable IP cores, designed for SYstem-on-chip (SOC) development. The IP cores are centered around a common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources.
標(biāo)簽： SYstem-on-chip integrated designed reusable
上傳時(shí)間： 2015-11-17
上傳用戶：D&L37
cc2420-A True SYstem-on-chip solution for 2.4 GHz IEEE 802.15.4 / ZigB
標(biāo)簽： SYstem-on-chip solution 2420 True
上傳時(shí)間： 2013-12-22
上傳用戶：15071087253
LCD Driver datasheet The SPF54126A, a 262144-color SYstem-on-chip (SoC) driver LSI designed for small and medium sizes of TFT LCD display, is capable of supporting up to 176xRGBx220 in resolution which can be achieved by the designated RAM for graphic data. The 528-channel source driver has true 6-bit resolution, which generates 64 Gamma-corrected values by an internal D/A converter. The source driver of SPFD54126A adopts OP-AMP structure to enhance display quality and it cooperates with advanced circuitry techniques to reduce power consumption.
標(biāo)簽： SYstem-on-chip datasheet designed Driver
上傳時(shí)間： 2016-09-22
上傳用戶：xauthu
Adaptive Techniques for Mixed Signal System on Chip
標(biāo)簽： Techniques Adaptive Signal System
上傳時(shí)間： 2017-04-15
上傳用戶：小寶愛考拉
Adaptive Techniques for Mixed Signal System on Chip - part 2
標(biāo)簽： Techniques Adaptive Signal System
上傳時(shí)間： 2014-01-16
上傳用戶：luopoguixiong
Adaptive Techniques for Mixed Signal System on Chip - part 3
標(biāo)簽： Techniques Adaptive Signal System
上傳時(shí)間： 2014-01-10
上傳用戶：dongqiangqiang
its bit the system on chip designed in verilog
標(biāo)簽： designed verilog system chip
上傳時(shí)間： 2017-08-02
上傳用戶：大融融rr
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