P3.18. An analog signal xa(t) = sin (100πt) is sampled using the following sampling intervals. In each case plot the spectrum of the resulting discrete-time signal. Ts= 0.1 ms, Ts= 1 ms, Ts = 0.01 Sec
標(biāo)簽： following intervals sampling sampled
上傳時(shí)間： 2017-07-12
上傳用戶：shizhanincc
FIR filter design with unseperable window, seperable window, frequency sampling method
標(biāo)簽： window unseperable seperable frequency
上傳時(shí)間： 2017-07-26
上傳用戶：chongcongying
adc converter, sampling and cuantization code
標(biāo)簽： cuantization converter sampling code
上傳時(shí)間： 2013-12-10
上傳用戶：lingzhichao
Sampling Delta-Sigma Audio DACMICRF102是Micrel公司新近推出的遠(yuǎn)距離無線數(shù)據(jù)發(fā)射芯片。該芯片采用Micrel公司最新的快速無線傳輸技術(shù),可實(shí)現(xiàn)真正的“數(shù)
標(biāo)簽： MICRF 102 數(shù)據(jù)手冊(cè)
上傳時(shí)間： 2013-04-24
上傳用戶：hebmuljb
Abstract: This application note describes the essential workings of an electrocardiogram (ECG). It discussesfactors that disrupt the ECG signals and make reliable, highly-accurate electrical characterization difficult. Theindustry-standard solution for ECG electrical characterization, which uses an analog front-end and ADCcombination, is explained. The article then introduces the MAX11040 simultaneous-sampling, sigma-deltaADC as a compelling, highly integrated solution that eliminates the need for the AFE, and saves both spaceand cost for the application.
標(biāo)簽： ADC 24位 心電圖 中的應(yīng)用
上傳時(shí)間： 2013-12-23
上傳用戶：sssl
Abstract: This application note describes how sampling clock jitter (time interval error or "TIE jitter") affectsthe performance of delta-sigma digital-to-analog converters (DACs). New insights explain the importanceof separately specifying low-frequency (< 2x passband frequency) and high-frequency or wideband (> 2xpassband frequency) jitter tolerance in these devices. The article also provides an application example ofa simple highly jittered cycle-skipped sampling clock and describes a method for generating a properbroadband jittered clock. The document then goes on to compare Maxim's audio DAC jitter tolerance tocompetitor audio DACs. Maxim's exceptionally high jitter tolerance allows very simple and low-cost sampleclock implementations.
標(biāo)簽： DAC 音頻 數(shù)模轉(zhuǎn)換器 抖動(dòng)
上傳時(shí)間： 2013-10-25
上傳用戶：banyou
A complete design for a data acquisition card for the IBM PC is detailed in this application note. Additionally, C language code is provided to allow sampling of data at speed of more than 20kHz. The speed limitation is strictly based on the execution speed of the "C" data acquisition loop. A "Turbo" XT can acquire data at speeds greater than 20kHz. Machines with 80286 and 80386 processors can go faster than 20kHz. The computer that was used as a test bed in this application was an XT running at 4.77MHz and therefore all system timing and acquisition time measurements are based on a 4.77MHz clock speed.
標(biāo)簽： 1099 LTC 數(shù)據(jù) 采集板
上傳時(shí)間： 2013-10-29
上傳用戶：BOBOniu
ANALOG INPUT BANDWIDTH is a measure of the frequencyat which the reconstructed output fundamental drops3 dB below its low frequency value for a full scale input. Thetest is performed with fIN equal to 100 kHz plus integer multiplesof fCLK. The input frequency at which the output is −3dB relative to the low frequency input signal is the full powerbandwidth.APERTURE JITTER is the variation in aperture delay fromsample to sample. Aperture jitter shows up as input noise.APERTURE DELAY See Sampling Delay.BOTTOM OFFSET is the difference between the input voltagethat just causes the output code to transition to the firstcode and the negative reference voltage. Bottom Offset isdefined as EOB = VZT–VRB, where VZT is the first code transitioninput voltage and VRB is the lower reference voltage.Note that this is different from the normal Zero Scale Error.CONVERSION LATENCY See PIPELINE DELAY.CONVERSION TIME is the time required for a completemeasurement by an analog-to-digital converter. Since theConversion Time does not include acquisition time, multiplexerset up time, or other elements of a complete conversioncycle, the conversion time may be less than theThroughput Time.DC COMMON-MODE ERROR is a specification which appliesto ADCs with differential inputs. It is the change in theoutput code that occurs when the analog voltages on the twoinputs are changed by an equal amount. It is usually expressed in LSBs.
標(biāo)簽： Converter Defi ADC 轉(zhuǎn)換器
上傳時(shí)間： 2013-11-12
上傳用戶：pans0ul
The equal-area theorem●This is sinusoidal PWM (SPWM)●The equal-area theorem can be appliedto realize any shape of waveforms ●Natural sampling●Calculation based on equal-area criterion●Selected harmonic elimination●Regular sampling●Hysteresis-band control●Triangular wave comparison withfeedback control
上傳時(shí)間： 2013-11-22
上傳用戶：linyao
Abstract: This article discusses future trends in the design of smartphones and other consumer products. The discussion focuses onthe importance of integration, which saves valuable PCB space and drives down costs.
標(biāo)簽： 集成 智能手機(jī) 驅(qū)動(dòng)器
上傳時(shí)間： 2014-01-13
上傳用戶：lhw888
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