The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallelinterfaces in a single chip targeted at consumer, industrial, medical, and communicationmarkets. To optimize system power consumption, the LPC315x have multiple powerdomains and a very flexible Clock Generation Unit (CGU) that provides dynamic clockgating and Scaling.The LPC315x is implemented as multi-chip module with two side-by-side dies, one fordigital fuctions and one for analog functions, which include a Power Supply Unit (PSU),audio codec, RTC, and Li-ion battery charger.
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Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture
The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.
The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to Scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.
Some of the UltraScale architecture breakthroughs include:
• Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%
• Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability
• Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization
• 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard
• Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets
• Greatly enhanced DSP and packet handling
The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
This application note discusses a variety of approaches for interfacing analog signals to 5V powered systems. Synthesizing a "rail-to-rail" op amp and Scaling techniques for A/D converters are covered. A voltage-to-frequency converter, applicable where high resolution is required, is also presented.
PNG開放源接口 The interface has
been designed to be as simple and intuitive as possible. It supports plotting and reading in the RGB (red, green,
blue), HSV (hue, saturation, value/brightness) and CMYK (cyan, magenta, yellow, black) colour spaces, basic
shapes, Scaling, bilinear interpolation, full TrueType antialiased and rotated text support, bezier curves, opening
existing PNG images and more.
//
// Histogram Sample
// This sample shows how to use the Sample Grabber filter for video image processing.
// Conceptual background:
// A histogram is just a frequency count of every pixel value in the image.
// There are various well-known mathematical operations that you can perform on an image
// using histograms, to enhance the image, etc.
// Histogram stretch (aka automatic gain control):
// Stretches the image histogram to fill the entire range of values. This is a "point operation,"
// meaning each pixel is scaled to a new value, without examining the neighboring pixels. The
// histogram stretch does not actually require you to calculate the full histogram. The Scaling factor
// is calculated from the minimum and maximum values in the image.
The double-density DWT is an improvement upon the critically sampled DWT with important additional properties: (1) It employs one Scaling function and two distinct wavelets, which are designed to be offset from one another by one half, (2) The double-density DWT is overcomplete by a factor of two, and (3) It is nearly shift-invariant. In two dimensions, this transform outperforms the standard DWT in terms of denoising however, there is room for improvement because not all of the wavelets are directional. That is, although the double-density DWT utilizes more wavelets, some lack a dominant spatial orientation, which prevents them from being able to isolate those directions.
In this paper we present a classifier called bi-density twin support vector machines (BDTWSVMs) for data classification. In the training stage, BDTWSVMs first compute the relative density degrees for all training points using the intra-class graph whose weights are determined by a local Scaling heuristic strategy, then optimize a pair of nonparallel hyperplanes through two smaller sized support vector machine (SVM)-typed problems. In the prediction stage, BDTWSVMs assign to the class label depending
on the kernel density degree-based distances from each test point to the two hyperplanes. BDTWSVMs not only inherit good properties from twin support vector machines (TWSVMs) but also give good description for data points. The experimental results on toy as well as publicly available datasets
indicate that BDTWSVMs compare favorably with classical SVMs and TWSVMs in terms of generalization
