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Simulink-to-fpga

we will use the Spartan3 XC3S200 FPGA to design a specified counter using the language VHDL.

we will use the Spartan3 XC3S200 FPGA to design a specified counter using the language VHDL.

標(biāo)簽： the specified Spartan3 language

上傳時(shí)間： 2015-05-13

上傳用戶：youke111
基于simulink的uwb仿真 uwb.mdl: UWB model - open this to begin. uwb_lib.mdl: Library blocks for UWB mode

基于simulink的uwb仿真 uwb.mdl: UWB model - open this to begin. uwb_lib.mdl: Library blocks for UWB model. uwb_init.m: Initialization called before model is loaded. uwb_settings: Sets up structure containing system parameters ( uwb in workspace). uwb_imr.m: Initializes UWB channel impulse response. uwb_sv_*.m: Four M-files used to generate channel impulse responses (MAT files).

標(biāo)簽： mdl UWB uwb simulink

上傳時(shí)間： 2013-12-22

上傳用戶：gengxiaochao
RF amplifier matlab-simulink files. Requires RF toolbox to run.

RF amplifier matlab-simulink files. Requires RF toolbox to run.

標(biāo)簽： matlab-simulink amplifier Requires toolbox

上傳時(shí)間： 2013-11-30

上傳用戶：frank1234
My thesis entitled "fpga digital clock," immature, to enlighten

My thesis entitled "fpga digital clock," immature, to enlighten

標(biāo)簽： enlighten entitled immature digital

上傳時(shí)間： 2014-01-02

上傳用戶：hxy200501
hard disk drive spindle motor control simulink, show you how to keep the speed at a level

hard disk drive spindle motor control simulink, show you how to keep the speed at a level

標(biāo)簽： simulink control spindle drive

上傳時(shí)間： 2015-11-01

上傳用戶：ikemada
this a book about how to use fpga,it is very simply ,but is useful for developing fpga,

this a book about how to use fpga,it is very simply ,but is useful for developing fpga,

標(biāo)簽： fpga developing simply useful

上傳時(shí)間： 2015-11-12

上傳用戶：cjl42111
v2html - verilog to html converter 主要為FPGA和ASIC工作人員

v2html - verilog to html converter 主要為FPGA和ASIC工作人員

標(biāo)簽： converter verilog v2html html

上傳時(shí)間： 2014-01-03

上傳用戶：lunshaomo
PCI vhdl for Fpga designer to design PCI IP

PCI vhdl for Fpga designer to design PCI IP

標(biāo)簽： PCI designer design Fpga

上傳時(shí)間： 2016-03-06

上傳用戶：lijianyu172
AHB to PCI Structure for FPGA/Asic Designer

AHB to PCI Structure for FPGA/Asic Designer

標(biāo)簽： Structure Designer FPGA Asic

上傳時(shí)間： 2013-12-26

上傳用戶：壞壞的華仔
分析了MATLAB/Simulink 中DSP Builder 模塊庫(kù)在FPGA 設(shè)計(jì)中優(yōu)點(diǎn)

分析了MATLAB/Simulink 中DSP Builder 模塊庫(kù)在FPGA 設(shè)計(jì)中優(yōu)點(diǎn)，然后結(jié)合FSK 信號(hào)的產(chǎn)生原理，給出了如何利用DSP Builder 模塊庫(kù)建立FSK 信號(hào)發(fā)生器模型，以及對(duì)FSK 信號(hào)發(fā)生器模型進(jìn)行算法級(jí)仿真和生成VHDL 語(yǔ)言的方法，并在modelsim 中對(duì)FSK 信號(hào)發(fā)生器進(jìn)行RTL 級(jí)仿真，最后介紹了在FPGA 芯片中實(shí)現(xiàn)FSK 信號(hào)發(fā)生器的設(shè) 計(jì)方法。

標(biāo)簽： Simulink Builder MATLAB FPGA

上傳時(shí)間： 2013-11-29

上傳用戶：熊少鋒