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Single-Phase

ADPLL of high level phase locked loop

ADPLL of high level phase locked loop

標(biāo)簽： locked ADPLL level phase

上傳時(shí)間： 2016-12-04

上傳用戶：wpwpwlxwlx
A high-speed variable phase accumulator for an ADPLL architecture

A high-speed variable phase accumulator for an ADPLL architecture

標(biāo)簽： architecture accumulator high-speed variable

上傳時(shí)間： 2013-11-26

上傳用戶：wpt
A Top-Down Verilog-A Design on the digital phase-lockedmloop

A Top-Down Verilog-A Design on the digital phase-lockedmloop

標(biāo)簽： phase-lockedmloop Verilog-A Top-Down digital

上傳時(shí)間： 2013-12-02

上傳用戶：silenthink
A Stochastic Time-to-Digital Converter for Digital Phase-Locked Loops

A Stochastic Time-to-Digital Converter for Digital Phase-Locked Loops

標(biāo)簽： Time-to-Digital Phase-Locked Stochastic Converter

上傳時(shí)間： 2014-01-16

上傳用戶：ANRAN
Ethernet Services Attributes Phase

Ethernet Services Attributes Phase

標(biāo)簽： Attributes Ethernet Services Phase

上傳時(shí)間： 2013-12-13

上傳用戶：xhz1993
A Matlab code to plot the matched filter for 16-element linear array with constant phase weights on

A Matlab code to plot the matched filter for 16-element linear array with constant phase weights on transmit and receive LFM waveform parameters.計(jì)算具有收發(fā)線性調(diào)頻波形參數(shù)的相位權(quán)重的16單元線性匹配濾波器

標(biāo)簽： constant matched element weights

上傳時(shí)間： 2014-07-19

上傳用戶：siguazgb
wireless communication based on single chip

wireless communication based on single chip

標(biāo)簽： communication wireless single based

上傳時(shí)間： 2013-12-25

上傳用戶：lindor
Based on the frequency of single-chip design, can measure the number of low-frequency signal

Based on the frequency of single-chip design, can measure the number of low-frequency signal

標(biāo)簽： low-frequency single-chip frequency the

上傳時(shí)間： 2016-12-25

上傳用戶：彭玖華
有關(guān)RTL8201CP網(wǎng)絡(luò)芯片嵌入式設(shè)計(jì)的開(kāi)發(fā)文檔 SINGLE-CHIP/SINGLE-PORT 10/100M FAST ETHERNET PHYCEIVER (With Auto C

有關(guān)RTL8201CP網(wǎng)絡(luò)芯片嵌入式設(shè)計(jì)的開(kāi)發(fā)文檔 SINGLE-CHIP/SINGLE-PORT 10/100M FAST ETHERNET PHYCEIVER (With Auto Crossover) DATASHEET Rev. 1.21 12 October 2004 Track ID: JATR-1076-21

標(biāo)簽： SINGLE-CHIP SINGLE-PORT PHYCEIVER ETHERNET

上傳時(shí)間： 2017-01-05

上傳用戶：libinxny
psk to DPSK conversion (absolute phase shift keying to the relative phase shift keying conversion)

psk to DPSK conversion (absolute phase shift keying to the relative phase shift keying conversion)

標(biāo)簽： conversion keying phase shift

上傳時(shí)間： 2017-01-28

上傳用戶：kbnswdifs

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