This paper presents several low-latency mixed-timing FIFO (first-in–first-out) interfaces designs that interface systems on a chip working at different speeds. The connected systems can be either synchronous or asynchronous. The designs are then adapted to work between systems with very long interconnect delays, by migrating a single-clock solution by Carloni et al. (1999, 2000, and 2001) (for “latency-insensitive” protocols) to mixed-timing domains. The new designs can be made arbitrarily robust with regard to metastability and interface operating speeds. Initial simulations for both latency and throughput are promising.
標簽： mixed-timing low-latency interfaces first-out
上傳時間： 2015-10-08
上傳用戶：dapangxie
MSP-FET430P140 Demo - ADC12, Single Channel Rpt Mode, TA1 as Sample Trigger
標簽： MSP-FET Channel Trigger Single
上傳時間： 2015-10-10
上傳用戶：ryb
use MATLAB anasys single freedom system mechanism vibrancy experimentation
標簽： experimentation mechanism vibrancy freedom
上傳時間： 2015-10-13
上傳用戶：colinal
sso(single sign on)，單點登錄，在門戶網站和企業應用集成中起著舉足輕重的地位。
上傳時間： 2015-10-17
上傳用戶：日光微瀾
Single Carrier Frequency Domain Equalization Simulation(單載波頻域均衡仿真程序)
標簽： Equalization Simulation Frequency Carrier
上傳時間： 2015-10-17
上傳用戶：asdfasdfd
HDOJ 1047 One of the first users of BIT s new supercomputer was Chip Diller. He extended his exploration of powers of 3 to go from 0 to 333 and he explored taking various sums of those numbers. ``This supercomputer is great, remarked Chip. ``I only wish Timothy were here to see these results. (Chip moved to a new apartment, once one became available on the third floor of the Lemon Sky apartments on Third Street.)
標簽： supercomputer extended Diller explor
上傳時間： 2013-12-22
上傳用戶：黑漆漆
Input The first line of the input contains a single integer T (1 <= T <= 20), the number of test cases. Then T cases follow. The first line of each case contains N, and the second line contains N integers giving the time for each people to cross the river. Each case is preceded by a blank line. There won t be more than 1000 people and nobody takes more than 100 seconds to cross. Output For each test case, print a line containing the total number of seconds required for all the N people to cross the river. Sample Input 1 4 1 2 5 10 Sample Output 17
標簽： the contains integer number
上傳時間： 2015-10-27
上傳用戶：plsee
BGA CHIP PLACEMENT AND ROUTING RUL
標簽： PLACEMENT ROUTING CHIP BGA
上傳時間： 2015-11-05
上傳用戶：asdfasdfd
cp2101 usb to rs232 Chip 開發工具
上傳時間： 2015-11-09
上傳用戶：hgy9473
The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around a common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources.
標簽： system-on-chip integrated designed reusable
上傳時間： 2015-11-17
上傳用戶：D&L37
