A Java virtual machine instruction consists of an opcode Specifying the operation to be performed, followed by zero or more operands embodying values to be operated upon. This chapter gives details about the format of each Java virtual machine instruction and the operation it performs.
標簽： instruction Specifying operation performed
上傳時間： 2014-01-11
上傳用戶：yiwen213
A Java virtual machine instruction consists of an opcode Specifying the operation to be performed, followed by zero or more operands embodying values to be operated upon. This chapter gives details about the format of each Java virtual machine instruction and the operation it performs.
標簽： instruction Specifying operation performed
上傳時間： 2015-05-02
上傳用戶：daoxiang126
A Java virtual machine instruction consists of an opcode Specifying the operation to be performed, followed by zero or more operands embodying values to be operated upon. This chapter gives details about the format of each Java virtual machine instruction and the operation it performs.
標簽： instruction Specifying operation performed
上傳時間： 2015-05-02
上傳用戶：shawvi
A Java virtual machine instruction consists of an opcode Specifying the operation to be performed, followed by zero or more operands embodying values to be operated upon. This chapter gives details about the format of each Java virtual machine instruction and the operation it performs.
標簽： instruction Specifying operation performed
上傳時間： 2013-12-12
上傳用戶：朗朗乾坤
There are three ways of Specifying an immediate dump Immediate dumps can be specified using the ALTER SESSION command ALTER SESSION SET EVENTS immediate trace name dump level level Immediate dumps can be specified in ORADEBUG ORADEBUG DUMP dump level
標簽： Specifying Immediate immediate specified
上傳時間： 2014-01-17
上傳用戶：mpquest
Abstract: This application note describes how sampling clock jitter (time interval error or "TIE jitter") affectsthe performance of delta-sigma digital-to-analog converters (DACs). New insights explain the importanceof separately Specifying low-frequency (< 2x passband frequency) and high-frequency or wideband (> 2xpassband frequency) jitter tolerance in these devices. The article also provides an application example ofa simple highly jittered cycle-skipped sampling clock and describes a method for generating a properbroadband jittered clock. The document then goes on to compare Maxim's audio DAC jitter tolerance tocompetitor audio DACs. Maxim's exceptionally high jitter tolerance allows very simple and low-cost sampleclock implementations.
上傳時間： 2013-10-25
上傳用戶：banyou
Abstract: Most magnetic read head data sheets do not fully specify the frequency-dependent components andare often vague when Specifying other key parameters. In some cases, the specifications of two very similarheads from two different manufacturers might be quite different in terms of parameters specified and omitted.The limitations in the data sheets make designing an optimum card reading system unnecessarily difficult andtime consuming. This document outlines a strategy to overcome the above shortcomings and offers guidelinesto overcome the noise issues.
上傳時間： 2013-11-13
上傳用戶：dysyase
Specifying the right reference and applying it correctly isa more difficult task than one might first surmise, consideringthat references are only 2- or 3-terminal devices.Although the word “accuracy” is most often spoken inreference to references, it is dangerous to use this wordtoo freely because it can mean different things to differentpeople. Even more perplexing is the fact that a referenceclassified as a dog in one application is a panacea inanother. This application note will familiarize the readerwith the various aspects of reference “accuracy” andpresent some tips on extracting maximum performancefrom any reference.
標簽： 電壓基準
上傳時間： 2013-10-15
上傳用戶：liuwei6419
完整性高的FPGA-PCB系統化協同設計工具 Cadence OrCAD and Allegro FPGA System Planner便可滿足較復雜的設計及在設計初級產生最佳的I/O引腳規劃，并可透過FSP做系統化的設計規劃，同時整合logic、schematic、PCB同步規劃單個或多個FPGA pin的最佳化及layout placement，借由整合式的界面以減少重復在design及PCB Layout的測試及修正的過程及溝通時間，甚至透過最佳化的pin mapping、placement后可節省更多的走線空間或疊構。 Specifying Design Intent 在FSP整合工具內可直接由零件庫選取要擺放的零件，而這些零件可直接使用PCB內的包裝，預先讓我們同步規劃FPGA設計及在PCB的placement。
標簽： Allegro Planner System FPGA
上傳時間： 2013-11-06
上傳用戶：wwwe
完整性高的FPGA-PCB系統化協同設計工具 Cadence OrCAD and Allegro FPGA System Planner便可滿足較復雜的設計及在設計初級產生最佳的I/O引腳規劃，并可透過FSP做系統化的設計規劃，同時整合logic、schematic、PCB同步規劃單個或多個FPGA pin的最佳化及layout placement，借由整合式的界面以減少重復在design及PCB Layout的測試及修正的過程及溝通時間，甚至透過最佳化的pin mapping、placement后可節省更多的走線空間或疊構。 Specifying Design Intent 在FSP整合工具內可直接由零件庫選取要擺放的零件，而這些零件可直接使用PCB內的包裝，預先讓我們同步規劃FPGA設計及在PCB的placement。
標簽： Allegro Planner System FPGA
上傳時間： 2013-10-19
上傳用戶：shaojie2080
