SMC takes a State machine stored in a .sm file and generates a State pattern in twelve programming languages. Includes: default transitions, transition args, transition guards, push/pop transitions and Entry/Exit actions. See User Manual for more info.
標(biāo)簽： programming generates machine pattern
上傳時間： 2013-12-25
上傳用戶：gaome
this program solves the steady-State navier-stokes eqn in 2d for the flow in a driven cavity problem. the function solved for is the streamfunction. the velocity may be obtained by differentiating the streamfunction.
標(biāo)簽： navier-stokes steady-State the program
上傳時間： 2014-01-06
上傳用戶：himbly
advantage of Channel State information at Txer
標(biāo)簽： information advantage Channel State
上傳時間： 2017-05-22
上傳用戶：66666
State flow program in Matlab simulink.
標(biāo)簽： simulink program Matlab State
上傳時間： 2017-05-23
上傳用戶：hn891122
kalman filter with State constraints lecture and example
標(biāo)簽： constraints example lecture kalman
上傳時間： 2013-12-02
上傳用戶：gxmm
GPIO (General Purpose Input and Output ports) with microprocessor programmable tri-State bus interface
標(biāo)簽： microprocessor programmable tri-State General
上傳時間： 2017-06-13
上傳用戶：hxy200501
用狀態(tài)機實現(xiàn)密碼鎖State machine used to achieve code lock
標(biāo)簽： machine achieve State code
上傳時間： 2017-06-21
上傳用戶：a673761058
This volume presents the State of the art concerning quality and interestingness measures for data mining. The book summarizes recent developments and presents original research on this topic. The chapters include surveys, comparative studies of existing measures, proposals of new measures, simulations, and case studies. Both theoretical and applied chapters are included. Papers for this book were selected and reviewed for correctness and completeness by an international review committee.
標(biāo)簽： interestingness concerning the presents
上傳時間： 2014-01-19
上傳用戶：ve3344
LMS: Least Mean Square the source code for State space environment.
標(biāo)簽： environment Square source Least
上傳時間： 2013-12-25
上傳用戶：xzt
Designing a synchronous finite State machine (FSM) is a common task for a digital logic engineer. This paper discusses a variety of issues regarding FSM design using Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and different methodologies are compared using real-world examples.
標(biāo)簽： synchronous Designing engineer digital
上傳時間： 2014-01-17
上傳用戶：dreamboy36
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