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usb_cpld_code.zip usbjtag - Variations on the implementation of a USB JTAG adapter.
標(biāo)簽： implementation usb_cpld_code Variations adapter
上傳時(shí)間： 2013-08-31
上傳用戶：ruan2570406
something useful for communication,source code based on FPGA
標(biāo)簽： communication something useful source
上傳時(shí)間： 2013-08-31
上傳用戶：maizezhen
On the design of an FPGA-Based OFDM modulator for IEEE 802.11a
標(biāo)簽： FPGA-Based modulator 802.11 design
上傳時(shí)間： 2013-09-02
上傳用戶：zjwangyichao
The DSP Design Flow workshop provides an introduction to the advanced tools you need to design and implement DSP algorithms targeting FPGAs. This intermediate workshop in implementing DSP functions focuses on learning how to use System Generator for DSP,
標(biāo)簽： workshop provides Design Flow
上傳時(shí)間： 2013-09-02
上傳用戶：joheace
Building a RISC System in an FPGA
標(biāo)簽： Building System RISC FPGA
上傳時(shí)間： 2013-09-04
上傳用戶：朗朗乾坤
本設(shè)計(jì)的基本要求是以復(fù)雜可編程邏輯器件CPLD為基礎(chǔ)，通過在EDA系統(tǒng)軟件ispDesignExpert System 環(huán)境下進(jìn)行數(shù)字系統(tǒng)設(shè)計(jì)，熟練掌握該環(huán)境下的功能仿真，時(shí)間仿真，管腳鎖定和芯片下載。 本系統(tǒng)基本上比較全面的模擬了計(jì)數(shù)式數(shù)字頻率計(jì)，廣泛應(yīng)用于工業(yè)、民用等各個(gè)領(lǐng)域，具有一定的開發(fā)價(jià)值。
標(biāo)簽： ispDesignExpert System EDA 系統(tǒng)軟件
上傳時(shí)間： 2013-09-05
上傳用戶：文993
System will automatically delete the directory
標(biāo)簽： automatically directory System delete
上傳時(shí)間： 2013-09-09
上傳用戶：toyoad
protel s help on line
上傳時(shí)間： 2013-09-18
上傳用戶：iswlkje
本文簡(jiǎn)單討論并總結(jié)了VHDL、Verilog，System verilog 這三中語言的各自特點(diǎn)和區(qū)別As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.
標(biāo)簽： Verilog verilog System VHDL
上傳時(shí)間： 2013-10-16
上傳用戶：牛布牛
Introduce High-Speed Digital System Design.
標(biāo)簽： High-Speed Digital Design System
上傳時(shí)間： 2013-10-20
上傳用戶：gps6888
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