Stereo-Vision circuit description, Aug 2002,
Ahmad Darabiha
This design contains four TOP level circuits: sv_chip0.vhd, sv_chip1.vhd, sv_chip2.vhd and
sv_chip3.vhd each of them built by one Virtex2000E fpga chip. This design is hierarchical and the
sub-circuits can be used as smaller benchmarks.
標簽：
Stereo-Vision
description
Darabiha
contains
上傳時間：
2017-03-19
上傳用戶：comua
