Joey is j2me client server application for for mobile platform. Build on TOP j2mepolish
標(biāo)簽： application j2mepolish for platform
上傳時(shí)間： 2016-09-29
上傳用戶：sz_hjbf
3D Statistical shape analysis by SHPARM method: code and paper. From the TOP group at UNC.
標(biāo)簽： Statistical analysis SHPARM method
上傳時(shí)間： 2016-10-20
上傳用戶：wfl_yy
iic總線控制器VHDL實(shí)現(xiàn) -- VHDL Source Files: i2c.vhd -- TOP level file i2c_control.vhd -- control function for the I2C master/slave shift.vhd -- shift register uc_interface.vhd -- uC interface function for an 8-bit 68000-like uC upcnt4.vhd -- 4-bit up counter i2c_timesim.vhd -- post-route I2C simulation netlist
標(biāo)簽： VHDL c_control vhd control
上傳時(shí)間： 2016-10-30
上傳用戶：woshiayin
TOP module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
標(biāo)簽： SHIFTER name module Input
上傳時(shí)間： 2013-12-13
上傳用戶：himbly
TOP module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
標(biāo)簽： SHIFTER name module Input
上傳時(shí)間： 2014-01-20
上傳用戶：三人用菜
The DSKs or eZdspTM LF2407 and the DMC1500 make up a table TOP motor development system which allows engineers and software developers to evaluate certain characteristics of the TMS320F240, TMS320F243, and TMS320LF2407 DSPs to determine if the processor meets the designers application requirements. Evaluators can create software to execute onboard or expand the system in a variety of ways.
標(biāo)簽： development eZdspTM system allow
上傳時(shí)間： 2013-12-24
上傳用戶：zhuoying119
英文 網(wǎng)絡(luò)課件 Computer Networking: A TOP Down Approach Featuring the Internet, 3rd edition. Jim Kurose, Keith Ross Addison-Wesley, July 2004.
標(biāo)簽： Networking Featuring Computer Approach
上傳時(shí)間： 2014-07-24
上傳用戶：123啊
A TOP-Down Verilog-A Design on the digital phase-lockedmloop
標(biāo)簽： phase-lockedmloop Verilog-A TOP-Down digital
上傳時(shí)間： 2013-12-02
上傳用戶：silenthink
FPGA程序的TOP.v文件，主要實(shí)現(xiàn)DDS信號(hào)發(fā)生器功能，通過(guò)定時(shí)器，可簡(jiǎn)單實(shí)現(xiàn)輸出幅值無(wú)極跳變
上傳時(shí)間： 2013-11-26
上傳用戶：曹云鵬
本程序包含：EEPROM的功能模型(eeprom.v)、讀/寫EEPROM的verilog HDL 行為模塊（eeprom_wr.v）、信號(hào)產(chǎn)生模塊（signal.v）和頂層模塊(TOP.v) ，這樣可以有一個(gè)完整的EEPROM的控制模塊和測(cè)試文件，本文件通過(guò)測(cè)試。
標(biāo)簽： EEPROM eeprom_wr verilog eeprom
上傳時(shí)間： 2017-01-22
上傳用戶：lanjisu111
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