精品国产第一福利网站,超碰在线99,色婷婷久久久久swag精品

Timer-A

This is a document for CYCLONE Develop Kits type LJ-FN300 FPGANIOS. Wish this would help you to find

This is a document for CYCLONE Develop Kits type LJ-FN300 FPGANIOS. Wish this would help you to find what kits can be select to use.

標(biāo)簽： FPGANIOS document CYCLONE Develop

上傳時間： 2013-08-16

上傳用戶：563686540
This brief introduce a kind of the framework construction to materialize the system. And an example

This brief introduce a kind of the framework construction to materialize the system. And an example was given with the discussion on the performence.

標(biāo)簽： construction materialize introduce framework

上傳時間： 2013-08-17

上傳用戶：ysystc699
this is a sample about usb out transmission

this is a sample about usb out transmission,it s default installation is D:\\RedLogic\\RCII_samples, and the software environment is quatrusII 5.0,it is usefull for studying hardware and usb.

標(biāo)簽： transmission sample about this

上傳時間： 2013-08-24

上傳用戶：座山雕牛逼
一篇關(guān)于CORDIC的文章A survey of CORDIC algorithms for FPGA based computers

一篇關(guān)于CORDIC的文章A survey of CORDIC algorithms for FPGA based computers

標(biāo)簽： CORDIC algorithms computers survey

上傳時間： 2013-08-31

上傳用戶：lliuhhui
采用FPGA模擬高動態(tài)GPS信號源中的C／A碼產(chǎn)生器

本文：采用了FPGA方法來模擬高動態(tài)(Global Position System GPS)信號源中的C／A碼產(chǎn)生器。C／A碼在GPS中實現(xiàn)分址、衛(wèi)星信號粗捕和精碼(P碼)引導(dǎo)捕獲起著重要的作用，通過硬件描述語言VERILOG在ISE中實現(xiàn)電路生成，采用MODELSIM、SYNPLIFY工具分別進(jìn)行仿真和綜合。

標(biāo)簽： FPGA GPS 模擬動態(tài)

上傳時間： 2013-08-31

上傳用戶：pwcsoft
usb_cpld_code.zip usbjtag - Variations on the implementation of a USB JTAG adapter.

usb_cpld_code.zip usbjtag - Variations on the implementation of a USB JTAG adapter.

標(biāo)簽： implementation usb_cpld_code Variations adapter

上傳時間： 2013-08-31

上傳用戶：ruan2570406
一種用CPLD設(shè)計GPS數(shù)字通道相關(guān)器中C／A碼產(chǎn)生囂的方法

摘要本文介紹了一種用CPLD設(shè)計GPS數(shù)字通道相關(guān)器中C／A碼產(chǎn)生囂的方法，詳細(xì)分析了設(shè)計原理并給出了相應(yīng)的仿真結(jié)果．這種設(shè)計方法已在我們研制的GPS，GLONASS兼容機中得到實際應(yīng)用。

標(biāo)簽： CPLD GPS 數(shù)字

上傳時間： 2013-09-01

上傳用戶：wangdean1101
Building a RISC System in an FPGA

Building a RISC System in an FPGA

標(biāo)簽： Building System RISC FPGA

上傳時間： 2013-09-04

上傳用戶：朗朗乾坤
gerber-to-protel is a pdf file

gerber-to-protel is a pdf file ,which is used for convert bmp to pcb.

標(biāo)簽： gerber-to-protel file is

上傳時間： 2013-09-18

上傳用戶：liuxinyu2016
protel_lib-PIC16 is a protel lib file.

protel_lib-PIC16 is a protel lib file.

標(biāo)簽： protel_lib-PIC protel file lib

上傳時間： 2013-09-18

上傳用戶：hn891122