-
Multioutput monolithic regulators are easy to use and fi tinto spaces where multichip solutions cannot. Nevertheless,the popularity of multioutput regulators is temperedby a lack of options for input voltages above 30V andsupport of high output currents. The LT3692A fi lls thisgap with a dual monolithic regulator that operates frominputs up to 36V. It also includes a number of channeloptimization features that allow the LT3692A’s per-channelperformance to rival that of multichip solutions.
標(biāo)簽：
492
DN
降壓
溫度監(jiān)控
上傳時(shí)間：
2014-01-03
上傳用戶：Huge_Brother
-
The RT9018A/B is a high performance positive voltage regulator designed for use in applications requining very low Input voltage and very low dropout voltage at up to 3A(peak).
標(biāo)簽：
9018
datasheet
RT
上傳時(shí)間：
2013-10-10
上傳用戶：geshaowei
-
The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embeddedapplications. The ARM Cortex-M3 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC1850/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals. The ARMCortex-M3 CPU also includes an internal prefetch unit that supports speculativebranching.The LPC1850/30/20/10 include up to 200 kB of on-chip SRAM data memory, a quad SPIFlash Interface (SPIFI), a State Configuration Timer (SCT) subsystem, two High-speedUSB controllers, Ethernet, LCD, an external memory controller, and multiple digital andanalog peripherals.
標(biāo)簽：
Cortex-M
1850
LPC
內(nèi)核微控制器
上傳時(shí)間：
2014-12-31
上傳用戶：zhuoying119
-
The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of datamemory, advanced configurable peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals
標(biāo)簽：
4300
LPC
ARM
雙核微控制器
上傳時(shí)間：
2013-10-28
上傳用戶：15501536189
-
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html
Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture
The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.
The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.
Some of the UltraScale architecture breakthroughs include:
• Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%
• Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability
• Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization
• 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard
• Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets
• Greatly enhanced DSP and packet handling
The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽：
UltraScale
Xilinx
架構(gòu)
上傳時(shí)間：
2013-11-21
上傳用戶：wxqman
-
Nios II定制指令用戶指南：With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Using custom
instructions, you can reduce a complex sequence of standard instructions to a single instruction implemented in hardware. You can use this feature for a variety of applications, for example, to optimize software inner
loops for digital signal processing (DSP), packet header processing, and computation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphical user interface (GUI) used to add up to 256 custom instructions to the Nios II processor.
The custom instruction logic connects directly to the Nios II arithmetic logic unit (ALU) as shown in Figure 1–1.
標(biāo)簽：
Nios
定制
指令
用戶
上傳時(shí)間：
2013-10-12
上傳用戶：kang1923
-
This application note covers the design considerations of a system using the performance
features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The
design focuses on high system throughput through the AXI Interconnect core with F
MAX
and
area optimizations in certain portions of the design.
The design uses five AXI video direct memory access (VDMA) engines to simultaneously move
10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p
format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video
test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary
video timing signals. Data read by each AXI VDMA is sent to a common on-screen display
(OSD) core capable of multiplexing or overlaying multiple video streams to a single output video
stream. The output of the OSD core drives the DVI video display interface on the board.
Performance monitor blocks are added to capture performance data. All 10 video streams
moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are
controlled by a MicroBlaze™ processor.
The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the
Xilinx® ML605 Rev D evaluation board
標(biāo)簽：
XAPP
740
AXI
互聯(lián)
上傳時(shí)間：
2013-11-23
上傳用戶：shen_dafa
-
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
標(biāo)簽：
Modelling
Guide
Navy
VHDL
上傳時(shí)間：
2013-11-20
上傳用戶：pzw421125
-
a8259 可編程中斷控制 altera提供
The a8259 is designed to simplify the implementation of the interrupt interface in 8088 and 8086 based microcomputer systems. The device is known as a programmable interrupt controller. The a8259 receives and prioritizes up to 8 interrupts, and in the cascade mode, this can be expanded up to 64 interrupts. An asynchronous reset and a clock input have been added to improve operation and reliability.
標(biāo)簽：
8259
VHDL
代碼
上傳時(shí)間：
2015-01-02
上傳用戶：panpanpan
-
VC技術(shù)內(nèi)幕第五版_English.The 6.0 release of Visual C++ shows Microsoft s continued focus on Internet technologies and COM, which are key components of the new Windows Distributed interNet Application Architecture (DNA). In addition to supporting these platform initiatives, Visual C++ 6.0 also adds an amazing number of productivity-boosting features such as Edit And Continue, IntelliSense, AutoComplete, and code tips. These features take Visual C++ to a new level. We have tried to make sure that this book keeps you up to speed on the latest technologies being introduced into Visual C++.
標(biāo)簽：
Microsoft
continued
Internet
English
上傳時(shí)間：
2013-12-08
上傳用戶：lepoke
