通過以太網遠程配置Nios II 處理器 應用筆記
Firmware in embedded hardware systems is frequently updated over the Ethernet. For
embedded systems that comprise a discrete microprocessor and the devices it controls, the
firmware is the software image run by the microprocessor. When the embedded system
includes an FPGA, firmware updates include updates of the hardware image on the FPGA. If
the FPGA includes a Nios® II soft processor, you can upgrade both the Nios II processor—as
part of the FPGA image—and the software that the Nios II processor runs, in a single remote
configuration session.
面向Eclips的Nios II軟件構建工具手冊
The Nios® II Software Build Tools (SBT) for Eclipse™ is a set of plugins based on the
Eclipse™ framework and the Eclipse C/C++ development toolkit (CDT) plugins. The
Nios II SBT for Eclipse provides a consistent development platform that works for all
Nios II embedded processor systems. You can accomplish all Nios II software
development tasks within Eclipse, including creating, editing, building, running,
debugging, and profiling programs.
Nios II 軟件開發人員手冊中的緩存和緊耦合存儲器部分
Nios® II embedded processor cores can contain instruction and data caches. This
chapter discusses cache-related issues that you need to consider to guarantee that
your program executes correctly on the Nios II processor. Fortunately, most software
based on the Nios II hardware abstraction layer (HAL) works correctly without any
special accommodations for caches. However, some software must manage the cache
directly. For code that needs direct control over the cache, the Nios II architecture
provides facilities to perform the following actions:
Nios II定制指令用戶指南：With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Using custom
instructions, you can reduce a complex sequence of standard instructions to a single instruction implemented in hardware. You can use this feature for a variety of applications, for example, to optimize software inner
loops for digital signal processing (DSP), packet header processing, and computation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphical user interface (GUI) used to add up to 256 custom instructions to the Nios II processor.
The custom instruction logic connects directly to the Nios II arithmetic logic unit (ALU) as shown in Figure 1–1.
Nios II 系列處理器配置選項:This chapter describes the Nios® II Processor parameter editor in Qsys and SOPC Builder. The Nios II Processor parameter editor allows you to specify the processor features for a particular Nios II hardware system. This chapter covers the features of the Nios II processor that you can configure with the Nios II Processor parameter editor; it is not a user guide for creating complete Nios II processor systems.
This application note provides a functional description of VHDL source code for a N x N DigitalCrosspoint Switch. The code is designed with eight inputs and eight outputs in order to targetthe 128-macrocell CoolRunner™-II CPLD device but can be easily expanded to target higherdensity devices. To obtain the VHDL source code described in this document, go to sectionVHDL Code, page 5 for instructions.
This application note shows how a Xilinx CoolRunnerTM-II CPLD can be used as a simplelogical switch that can quickly and reliably select between different MPEG video sources. Thesource code for the design is available on the Xilinx website, and is linked from the “VHDLCode” section. The code can be expanded by the user to perform additional operations usingthe remaining CPLD resources
