UART 4 UART參考設計，Xilinx提供VHDL代碼 uart_VHDl
This zip file contains the following folders:
\VHDl_source -- Source VHDL files:
uart.VHD - top level file
txmit.VHD - transmit portion of uart
rcvr.VHD - - receive portion of uart
\VHDl_testfixture -- VHDL Testbench files. This files only include the testbench behavior, they
do not instantiate the DUT. This can easily be done in a top-level VHDL
file or a schematic. This folder contains the following files:
txmit_tb.VHD -- Test bench for txmit.VHD.
rcvr_tf.VHD -- Test bench for rcvr.VHD.
標簽：
UART
Xilinx
VHDL
參考設計
上傳時間：
2013-11-02
上傳用戶：18862121743
