-
賽靈思正式發(fā)貨全球首款異構(gòu) 3D FPGA，為 Nx100G 和 400G 線路卡解決方案帶來(lái)突破性集成能力
標(biāo)簽：
HT_Press_Pitch-Chinese-final
VIRTEX
上傳時(shí)間：
2013-10-11
上傳用戶(hù)：13033095779
-
本文是關(guān)于賽靈思Artix-7 FPGA 數(shù)據(jù)手冊(cè):直流及開(kāi)關(guān)特性的詳細(xì)介紹。
文章中也討論了以下問(wèn)題：
1.全新 Artix-7 FPGA 系列有哪些主要功能和特性?
Artix-7 系列提供了業(yè)界最低功耗、最低成本的 FPGA，采用了小型封裝，配合VIRTEX 架構(gòu)增強(qiáng)技術(shù)，能滿(mǎn)足小型化產(chǎn)品的批量市場(chǎng)需求，這也正是此前 Spartan 系列 FPGA 所針對(duì)的市場(chǎng)領(lǐng)域。與 Spartan-6 FPGA 相比，Artix-7 器件的邏輯密度從 20K 到 355K 不等，不但使速度提升 30%，功耗減半，尺寸減小 50%，而且價(jià)格也降了 35%。
2.Artix-7 FPGA 系列支持哪些類(lèi)型的應(yīng)用和終端市場(chǎng)?
Artix-7 FPGA 系列面向各種低成本、小型化以及低功耗的應(yīng)用，包括如便攜式超聲波醫(yī)療設(shè)備、軍用通信系統(tǒng)、高端專(zhuān)業(yè)/消費(fèi)類(lèi)相機(jī)的 DSLR 鏡頭模塊，以及航空視頻分配系統(tǒng)等。
標(biāo)簽：
Artix
FPGA
賽靈思
數(shù)據(jù)手冊(cè)
上傳時(shí)間：
2013-10-11
上傳用戶(hù)：zouxinwang
-
This application note describes how to retrieve user-defined data from Xilinx configurationPROMs (XC18V00 and Platform Flash devices) after the same PROM has configured theFPGA. The method to add user-defined data to the configuration PROM file is also discussed.The reference design described in this application note can be used in any of the followingXilinx FPGA architectures: Spartan™-II, Spartan-IIE, Spartan-3, VIRTEX™, VIRTEX-E, VIRTEX-II,and VIRTEX-II Pro.
標(biāo)簽：
XAPP
PROM
694
讀取
上傳時(shí)間：
2013-11-11
上傳用戶(hù)：zhouli
-
Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.
標(biāo)簽：
VIRTEX
FPGA
PCB
設(shè)計(jì)手冊(cè)
上傳時(shí)間：
2014-01-13
上傳用戶(hù)：竺羽翎2222
-
The exacting technological demands created byincreasing bandwidth requirements have given riseto significant advances in FPGA technology thatenable engineers to successfully incorporate highspeedI/O interfaces in their designs. One aspect ofdesign that plays an increasingly important role isthat of the FPGA package. As the interfaces get fasterand wider, choosing the right package has becomeone of the key considerations for the systemdesigner.
標(biāo)簽：
VIRTEX
247
WP
高級(jí)封裝
上傳時(shí)間：
2013-10-22
上傳用戶(hù)：1234xhb
-
The VIRTEX™-4 user access register (USR_ACCESS_VIRTEX4) is a 32-bit register thatprovides direct access to bitstream data by the FPGA fabric. It is useful for loadingPowerPC™ 405 (PPC405) processor caches and/or other data into the FPGA after the FPGAhas been configured, thus achieving partial reconfiguration. The USR_ACCESS_VIRTEX4register is programmed through the bitstream with a command that writes a series of 32-bitwords.
標(biāo)簽：
USR_ACCESS
PowerPC
XAPP
719
上傳時(shí)間：
2013-11-13
上傳用戶(hù)：我累個(gè)乖乖
-
Xilinx FPGAs require at least two power supplies: VCCINTfor core circuitry and VCCO for I/O interface. For the latestXilinx FPGAs, including VIRTEX-II Pro, VIRTEX-II and Spartan-3, a third auxiliary supply, VCCAUX may be needed. Inmost cases, VCCAUX can share a power supply with VCCO.The core voltages, VCCINT, for most Xilinx FPGAs, rangefrom 1.2V to 2.5V. Some mature products have 3V, 3.3Vor 5V core voltages. Table 1 shows the core voltagerequirement for most of the FPGA device families. TypicalI/O voltages (VCCO) vary from 1.2V to 3.3V. The auxiliaryvoltage VCCAUX is 2.5V for VIRTEX-II Pro and Spartan-3, andis 3.3V for VIRTEX-II.
標(biāo)簽：
Xilinx
FPGA
DC
輸出
上傳時(shí)間：
2013-10-22
上傳用戶(hù)：liu999666
-
This application note covers the design considerations of a system using the performance
features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The
design focuses on high system throughput through the AXI Interconnect core with F
MAX
and
area optimizations in certain portions of the design.
The design uses five AXI video direct memory access (VDMA) engines to simultaneously move
10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p
format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video
test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary
video timing signals. Data read by each AXI VDMA is sent to a common on-screen display
(OSD) core capable of multiplexing or overlaying multiple video streams to a single output video
stream. The output of the OSD core drives the DVI video display interface on the board.
Performance monitor blocks are added to capture performance data. All 10 video streams
moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are
controlled by a MicroBlaze™ processor.
The reference system is targeted for the VIRTEX-6 XC6VLX240TFF1156-1 FPGA on the
Xilinx® ML605 Rev D evaluation board
標(biāo)簽：
XAPP
740
AXI
互聯(lián)
上傳時(shí)間：
2013-11-14
上傳用戶(hù)：fdmpy
-
賽靈思推出業(yè)界首款自動(dòng)化精細(xì)粒度時(shí)鐘門(mén)控解決方案，該解決方案可將 VIRTEX®-6 和 Spartan®-6 FPGA 設(shè)計(jì)方案的動(dòng)態(tài)功耗降低高達(dá) 30%。賽靈思智能時(shí)鐘門(mén)控優(yōu)化可自動(dòng)應(yīng)用于整個(gè)設(shè)計(jì)，既無(wú)需在設(shè)計(jì)流程中添加更多新的工具或步驟，又不會(huì)改變現(xiàn)有邏輯或時(shí)鐘，從而避免設(shè)計(jì)修改。此外，在大多數(shù)情況下，該解決方案都能保留時(shí)序結(jié)果。
標(biāo)簽：
370
WP
智能時(shí)鐘
動(dòng)態(tài)
上傳時(shí)間：
2013-11-16
上傳用戶(hù)：eastimage
-
針對(duì)傳統(tǒng)集成電路（ASIC）功能固定、升級(jí)困難等缺點(diǎn)，利用FPGA實(shí)現(xiàn)了擴(kuò)頻通信芯片STEL-2000A的核心功能。使用ISE提供的DDS IP核實(shí)現(xiàn)NCO模塊，在下變頻模塊調(diào)用了硬核乘法器并引入CIC濾波器進(jìn)行低通濾波，給出了DQPSK解調(diào)的原理和實(shí)現(xiàn)方法，推導(dǎo)出一種簡(jiǎn)便的引入?仔/4固定相移的實(shí)現(xiàn)方法。采用模塊化的設(shè)計(jì)方法使用VHDL語(yǔ)言編寫(xiě)出源程序，在VIRTEX-II Pro 開(kāi)發(fā)板上成功實(shí)現(xiàn)了整個(gè)系統(tǒng)。測(cè)試結(jié)果表明該系統(tǒng)正確實(shí)現(xiàn)了STEL-2000A的核心功能。
Abstract:
To overcome drawbacks of ASIC such as fixed functionality and upgrade difficulty, FPGA was used to realize the core functions of STEL-2000A. This paper used the DDS IP core provided by ISE to realize the NCO module, called hard core multiplier and implemented CIC filter in the down converter, described the principle and implementation detail of the demodulation of DQPSK, and derived a simple method to introduce a fixed phase shift of ?仔/4. The VHDL source code was designed by modularity method , and the complete system was successfully implemented on VIRTEX-II Pro development board. Test results indicate that this system successfully realize the core function of the STEL-2000A.
標(biāo)簽：
STEL
2000
FPGA
擴(kuò)頻通信
上傳時(shí)間：
2013-11-06
上傳用戶(hù)：liu123
