Advanced ASIC Chip Synthesis Using Synopsys Design Compiler. This second edition of this book describes the advanced concepts and
techniques used towards ASIC chip synthesis, physical synthesis, formal
Verification and static timing analysis, using the Synopsys suite of tools.
The use of hardware description languages (HDLs) is becoming
increasingly common for designing and verifying FPGA designs.
Behavior level description not only increases design productivity, but also
provides unique advantages for design Verification. The most dominant
HDLs today are Verilog and VHDL. This application note illustrates the
use of Verilog in the design and Verification of a digital UART (Universal
Asynchronous Receiver & Transmitter).
The W78E58B is an 8-bit microcontroller which has an in-system programmable Flash EPROM for
firmware updating. The instruction set of the W78E58B is fully compatible with the standard 8052. The
W78E58B contains a 32K bytes of main ROM and a 4K bytes of auxiliary ROM which allows the
contents of the 32KB main ROM to be updated by the loader program located at the 4KB auxiliary
ROM 512 bytes of on-chip RAM four 8-bit bi-directional and bit-addressable I/O ports an additional 4-
bit port P4 three 16-bit timer/counters a serial port. These peripherals are supported by a eight
sources two-level interrupt capability. To facilitate programming and Verification, the ROM inside the
W78E58B allows the program memory to be programmed and read electronically. Once the code is
confirmed, the user can protect the code for security
The emphasis of this book is on real-time application of Synopsys tools, used
to combat various problems seen at VDSM geometries. Readers will be
exposed to an effective design methodology for handling complex, submicron
ASIC designs. Significance is placed on HDL coding styles,
synthesis and optimization, dynamic simulation, formal Verification, DFT
scan insertion, links to layout, physical synthesis, and static timing analysis.
At each step, problems related to each phase of the design flow are identified,
with solutions and work-around described in detail. In addition, crucial issues
related to layout, which includes clock tree synthesis and back-end
integration (links to layout) are also discussed at length. Furthermore, the
book contains in-depth discussions on the basics of Synopsys technology
libraries and HDL coding styles, targeted towards optimal synthesis solution.
The idea for this book was born during one of my project-related trips to the beautiful city
of Hangzhou in China, where in the role of Chief Architect I had to guide a team of very
young, very smart and extremely dedicated software developers and Verification engineers.
Soon it became clear that as eager as the team was to jump into the coding, it did not have
any experience in system architecture and design and if I did not want to spend all my time in
constant travel between San Francisco and Hangzhou, the only option was to groom a number
of local junior architects. Logically, one of the first questions being asked by these carefully
selected future architects was whether I could recommend a book or other learning material
that could speed up the learning cycle. I could not. Of course, there were many books on
various related topics, but many of them were too old and most of the updated information
was either somewhere on the Internet dispersed between many sites and online magazines, or
buried in my brain along with many years of experience of system architecture.
The Verilog Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable,it supports the development,Verification, synthesis,and testing of hardware designs; the communication of hardware design data; and the maintenance,modification,and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.
