Visual Assist X 10.6.1822.0（VC6.0智能插件）
標(biāo)簽： Visual Assist 1822 6.0
上傳時(shí)間： 2013-12-15
上傳用戶：ysystc670
MATLAB5[x]入門與提高.
標(biāo)簽： MATLAB5
上傳時(shí)間： 2014-01-25
上傳用戶：fairy0212
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-21
上傳用戶：wxqman
Allegro15[1].X培訓(xùn)教材
標(biāo)簽： Allegro 15 培訓(xùn)教材
上傳時(shí)間： 2014-01-08
上傳用戶：qzhcao
The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Specification Revision 2.0a ([Ref 6]) dictates that when a target signals adata transfer, "the target must do so within 16 clocks of the assertion of FRAME#." PCItermination transactions, such as Split Response/Complete, are commonly used to meet thelatency specifications. This method adds complexity to the design, as well as additional systemlatency. Another solution is to increase the ratio of the memory frequency to the PCI-X busfrequency. However, this solution increases the required power and clock resource usage.
上傳時(shí)間： 2013-11-24
上傳用戶：18707733937
支持X/YModem和cis_b+協(xié)議的串口通訊程序
標(biāo)簽： YModem cis_b 協(xié)議 串口通訊
上傳時(shí)間： 2014-01-17
上傳用戶：qweqweqwe
支持X/Y/Z Modem協(xié)議的傳輸文件的通訊程序
標(biāo)簽： Modem 協(xié)議 傳輸 通訊程序
上傳時(shí)間： 2015-01-03
上傳用戶：xg262122
X Windows下的迷宮程序
上傳時(shí)間： 2015-01-04
上傳用戶：372825274
支持Windows 3.x、Windows 9x平臺(tái)上的中文（GB、Big5）、日文（Shift JIS、EUC JIS)、韓文（KS C 5601）、HZ碼的顯示與輸入,智能內(nèi)碼識(shí)別，支持屏幕取詞翻譯的16位程序(VC1.5編譯)。作者：朱佳良
標(biāo)簽： Windows JIS Shift Big5
上傳時(shí)間： 2013-12-28
上傳用戶：003030
支持SSL v2/v3, TLS, PKCS #5, PKCS #7, PKCS #11, PKCS #12, S/MIME, X.509v3證書等安全協(xié)議或標(biāo)準(zhǔn)的開發(fā)庫(kù)編譯用到NSPR
上傳時(shí)間： 2014-01-27
上傳用戶：sammi
蟲蟲下載站版權(quán)所有 京ICP備2021023401號(hào)-1
