AstroII-EVB-F1K(A)-L144開發(fā)板用戶指南
標(biāo)簽： AstroII-EVB-F 144 開發(fā)板 用戶
上傳時間： 2013-11-08
上傳用戶：liuchee
cv181l-a-20
標(biāo)簽： Specification_V 181 1.0 L-A
上傳時間： 2013-10-20
上傳用戶：ikemada
Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective solution. Maxim's 3GPP TS25.104-compliant transceiver solution is presented along withcomplete radio reference designs such as RD2550. For more information on the RD2550, see reference design 5364, "FemtocellRadio Reference Designs Using the MAX2550–MAX2553 Transceivers."
標(biāo)簽： Base-Station Applications Single-Chip Transceiver
上傳時間： 2013-11-05
上傳用戶：超凡大師
This application note provides a detailed description of the Spartan™-3 configurationarchitecture. It explains the composition of the bitstream file and how this bitstream isinterpreted by the configuration logic to program the part. Additionally, a methodology ispresented that will guide the user through the readback process. This information can be usedfor partial reconfiguration or partial readback.
標(biāo)簽： Spartan XAPP 452 架構(gòu)
上傳時間： 2013-11-16
上傳用戶：qingdou
The PPC405 Virtex-4 is a wrapper around the Virtex-4PowerPC™ 405 Processor Block primitive. For detailsregarding the PowerPC 405, see the PowerPC 405 ProcessorBlock Reference Guide.
標(biāo)簽： Wrapper Virtex 306 405
上傳時間： 2015-01-02
上傳用戶：JIUSHICHEN
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
標(biāo)簽： Modelling Guide Navy VHDL
上傳時間： 2013-11-20
上傳用戶：pzw421125
program to trasmit data to a TI92 with the TI Graph-Link
標(biāo)簽： Graph-Link program trasmit data
上傳時間： 2015-01-03
上傳用戶：youke111
C詞法分析器實現(xiàn),AOE網(wǎng)絡(luò)算法實現(xiàn),KRUSKAL算法實現(xiàn),PRIM算法實現(xiàn),計算機(jī)圖形學(xué)影線填充算法（鍵盤坐標(biāo)輸入）,計算機(jī)圖形學(xué)影線填充算法（鼠標(biāo)輸入）,人工智能A*算法實現(xiàn)的C語言程序
上傳時間： 2015-01-05
上傳用戶：hwl453472107
一個利用中斷修改后進(jìn)行的A/D采集功能的使用軟件.
上傳時間： 2015-01-06
上傳用戶：LIKE
CSL is a programming language with C syntax and comprehensive libraries. The compact scripting engine can also be embedded into your own applications as a powerful macro language. Windows Distribution utilities.
標(biāo)簽： comprehensive programming libraries scripting
上傳時間： 2013-11-27
上傳用戶：xuanchangri
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