亚洲欧美第一页_禁久久精品乱码_粉嫩av一区二区三区免费野_久草精品视频

蟲(chóng)蟲(chóng)首頁(yè)| 資源下載| 資源專輯| 精品軟件
登錄| 注冊(cè)

aSynchronous

  • This article discuss the Globally aSynchronous and Locally Synchronous system.

    This article discuss the Globally aSynchronous and Locally Synchronous system.

    標(biāo)簽: aSynchronous Synchronous Globally Locally

    上傳時(shí)間: 2017-06-04

    上傳用戶:kelimu

  • This paper will discuss the design of an aSynchronous FIFO,aSynchronous FIFOs are widely used in the

    This paper will discuss the design of an aSynchronous FIFO,aSynchronous FIFOs are widely used in the computer networking industry to receive data at a particular frequency and transmit them at another frequency. An aSynchronous FIFO has two different clocks: one for read and one for write.

    標(biāo)簽: aSynchronous aSynchronous the discuss

    上傳時(shí)間: 2013-12-09

    上傳用戶:Thuan

  • aSynchronous receiver

    aSynchronous receiver

    標(biāo)簽: aSynchronous receiver

    上傳時(shí)間: 2013-12-07

    上傳用戶:exxxds

  • An aSynchronous transmitter to be used in digital oscilloscope

    An aSynchronous transmitter to be used in digital oscilloscope

    標(biāo)簽: aSynchronous oscilloscope transmitter digital

    上傳時(shí)間: 2017-07-02

    上傳用戶:cjf0304

  • Simulation and Synthesis Techniques for aSynchronous FIFO Design with aSynchronous Pointer Comparis

    Simulation and Synthesis Techniques for aSynchronous FIFO Design with aSynchronous Pointer Comparisons

    標(biāo)簽: aSynchronous Simulation Techniques Synthesis

    上傳時(shí)間: 2017-07-19

    上傳用戶:Zxcvbnm

  • Bitrate adaptation standard V.110 (aSynchronous data transmission over ISDN)

    Bitrate adaptation standard V.110 (aSynchronous data transmission over ISDN)

    標(biāo)簽: aSynchronous transmission adaptation standard

    上傳時(shí)間: 2017-07-21

    上傳用戶:水口鴻勝電器

  • This paper analyzes the vector control theory of aSynchronous motors based on the magnetic orientati

    This paper analyzes the vector control theory of aSynchronous motors based on the magnetic orientation of motor rotors, and its mathematical model is made. Then the variable frequency vector speed-adjusting experimental system is built with the DSP TMS320F2812 which works as the core control chip and intelligent power module.

    標(biāo)簽: aSynchronous orientati the analyzes

    上傳時(shí)間: 2013-12-08

    上傳用戶:shinesyh

  • Efficient aSynchronous Bundled-data Pipelines for DCT Matrix-Vector Multiplication

    Efficient aSynchronous Bundled-data Pipelines for DCT Matrix-Vector Multiplication

    標(biāo)簽: Multiplication Matrix-Vector aSynchronous Bundled-data

    上傳時(shí)間: 2017-09-19

    上傳用戶:cuiyashuo

  • A Scalable Counterflow-Pipelined aSynchronous Radix-4 Booth Multiplier

    A Scalable Counterflow-Pipelined aSynchronous Radix-4 Booth Multiplier

    標(biāo)簽: Counterflow-Pipelined aSynchronous Multiplier Scalable

    上傳時(shí)間: 2014-01-04

    上傳用戶:jjj0202

  • 基于FPGA的通用異步收發(fā)器的設(shè)計(jì).rar

    通用異步收發(fā)器(Universal aSynchronous Receiver Transmitter,UART)是一種能同時(shí)支持短距離和長(zhǎng)距離數(shù)據(jù)傳輸?shù)拇型ㄐ沤涌冢粡V泛應(yīng)用于微機(jī)和外設(shè)之間的數(shù)據(jù)交換。像8251、NS8250、NS16550等都是常用的UART芯片,但是這些專用的串行接口芯片的缺點(diǎn)是數(shù)據(jù)傳輸速率比較慢,難以滿足高速率數(shù)據(jù)傳輸?shù)膱?chǎng)合,而更重要的就是它們都具有不可移植性,因此要利用這些芯片來(lái)實(shí)現(xiàn)PC機(jī)和FPGA芯片之間的通信,勢(shì)必會(huì)增加接口連線的復(fù)雜程度以及降低整個(gè)系統(tǒng)的穩(wěn)定性和有效性。 本課題就是針對(duì)UART的特點(diǎn)以及FPGA設(shè)計(jì)具有可移植性的優(yōu)勢(shì),提出了一種基于FPGA芯片的嵌入式UART設(shè)計(jì)方法,其中主要包括狀態(tài)機(jī)的描述形式以及自頂向下的設(shè)計(jì)方法,利用硬件描述語(yǔ)言來(lái)編制UART的各個(gè)子功能模塊以及頂層模塊,之后將其集成到FPGA芯片的內(nèi)部,這樣不僅能解決傳統(tǒng)UART芯片的缺點(diǎn)而且同時(shí)也使整個(gè)系統(tǒng)變得更加具有緊湊性以及可靠性。 本課題所設(shè)計(jì)的LIART支持標(biāo)準(zhǔn)的RS-232C傳輸協(xié)議,主要設(shè)計(jì)有發(fā)送模塊、接收模塊、線路控制與中斷仲裁模塊、Modem控制模塊以及兩個(gè)獨(dú)立的數(shù)據(jù)緩沖區(qū)FIFO模塊。該模塊具有可變的波特率、數(shù)據(jù)幀長(zhǎng)度以及奇偶校驗(yàn)方式,還有多種中斷源、中斷優(yōu)先級(jí)、較強(qiáng)的抗干擾數(shù)據(jù)接收能力以及芯片內(nèi)部自診斷的能力,模塊內(nèi)分開(kāi)的接收和發(fā)送數(shù)據(jù)緩沖寄存器能實(shí)現(xiàn)全雙工通信。除此之外最重要的是利用IP模塊復(fù)用技術(shù)設(shè)計(jì)數(shù)據(jù)緩沖區(qū)FIFO,采用兩種可選擇的數(shù)據(jù)緩沖模式。這樣既可以應(yīng)用于高速的數(shù)據(jù)傳輸環(huán)境,也能適合低速的數(shù)據(jù)傳輸場(chǎng)合,因此可以達(dá)到資源利用的最大化。 在具體的設(shè)計(jì)過(guò)程中,利用Synplify Pro綜合工具、ModelSim仿真工具、ISE集成的軟件開(kāi)發(fā)環(huán)境中對(duì)各個(gè)功能模塊進(jìn)行綜合優(yōu)化、仿真驗(yàn)證以及下載實(shí)現(xiàn)。各項(xiàng)數(shù)據(jù)結(jié)果表明,本課題中所設(shè)計(jì)的UART滿足預(yù)期設(shè)計(jì)目標(biāo)。

    標(biāo)簽: FPGA 異步收發(fā)器

    上傳時(shí)間: 2013-08-02

    上傳用戶:rocketrevenge

主站蜘蛛池模板: 南溪县| 湖南省| 南丹县| 淄博市| 北宁市| 浦江县| 武穴市| 阜新市| 章丘市| 定边县| 房产| 鹤峰县| 汶川县| 台南市| 蒙自县| 阿鲁科尔沁旗| 肥东县| 临泽县| 鹿邑县| 南召县| 澎湖县| 荣成市| 西青区| 安乡县| 丽水市| 繁昌县| 江口县| 英超| 周口市| 屯昌县| 舞阳县| 舒兰市| 高青县| 恩施市| 荔浦县| 乌海市| 吴川市| 祁阳县| 双城市| 铅山县| 东平县|