What is New in C51 Version 8.18[Device Support]added debug support for the NXP P89LPC9408 in the LPC900 EPM Emulator/Programmer.[New Supported Device]Nuvoton W681308 device.[New Supported Device]NXP P89LPC9201, P89LPC9211, P89LPC922A1, P89LPC9241, P89LPC9251, P89LPC9301, P89LPC931A1, P89LPC9331, P89LPC9341, and P89LPC9351 devices.[New Supported Device]SiLabs C8051F500, C8051F501, C8051F504, C8051F505, C8051F506, C8051F507, C8051F508, C8051F509, C8051F510, and C8051F511 devices.[ULINK2 Support]Corrected potential deadlock on ST uPSD targets.[Device Simulation]Corrected simulation of Infineon XC800 MDU.[Device Simulation]Corrected behaviour of EXFn and TOGn on SiLabs C8051F12x/F13x devices.[Device Simulation]added simulation for Atmel AT89C51RE2, including simulation of second UART.[Cx51 Compiler]Corrected failed initialization on far addresses when the object is located with _at_. 本資料僅供學習評估之用,請勿用于商業用途!請在學習評估24小時內刪除.
上傳時間： 2013-11-01
上傳用戶：panpanpan
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上傳時間： 2013-11-14
上傳用戶：fdmpy
a8259 可編程中斷控制 altera提供 The a8259 is designed to simplify the implementation of the interrupt interface in 8088 and 8086 based microcomputer systems. The device is known as a programmable interrupt controller. The a8259 receives and prioritizes up to 8 interrupts, and in the cascade mode, this can be expanded up to 64 interrupts. An asynchronous reset and a clock input have been added to improve operation and reliability.
上傳時間： 2014-11-29
上傳用戶：zhyiroy
This application note describes a reference system which illustrates how to build an embeddedPowerPC® system using the Xilinx 1-Gigabit Ethernet Media Access Controller processor core.This system has the PLB_Gemac configured to use Scatter/Gather Direct Memory Access andthe Serializer/Deserializer (SerDes) interface. This application note describes how to set up thespecific clocking structure required for the SerDes interface and the constraints to be added tothe UCF file. This reference system is complete with a standalone software application to testsome of the main features of this core, including access to registers, DMA capabilities, transmitand receive in loopback mode. This reference system is targeted for the ML300 evaluationboard.
上傳時間： 2013-11-01
上傳用戶：truth12
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上傳時間： 2013-11-23
上傳用戶：shen_dafa
a8259 可編程中斷控制 altera提供 The a8259 is designed to simplify the implementation of the interrupt interface in 8088 and 8086 based microcomputer systems. The device is known as a programmable interrupt controller. The a8259 receives and prioritizes up to 8 interrupts, and in the cascade mode, this can be expanded up to 64 interrupts. An asynchronous reset and a clock input have been added to improve operation and reliability.
上傳時間： 2015-01-02
上傳用戶：panpanpan
手機文件瀏覽器 Here are the sources to SMan v1.2c 1.2 is a major jump from v1.1. You will see this from the way the code has been restructured into multiple files. It also supports flip closed. However, to my chagrin, I made the mistake of assuming there will only be one flip closed view. :( That s changed in v1.3 :) 1.3 supports multiple flip closed views that can be easily added into SMan.
上傳時間： 2015-03-31
上傳用戶：彭玖華
This toolbox distributes processes over matlab workers available over the intranet/internet (SPMD or MPMD parallel model). It is very useful for corsely granular parallelization problems and in the precesence of a distributed and heterogeneus computer enviroment. No need for configuration files ! Cross platforms, cross OS and cross MATLAB versions. Workers can be added to the parallel computation even if it has started. No need of a common file system, all comms are using tcpip connections
標簽： over distributes available processes
上傳時間： 2014-01-03
上傳用戶：希醬大魔王
*** *** *** *** *** *** *** *** *** *** *** *** *** *** *** *** *** *** ** RELEASE NOTES *** *** *** *** ***** *** *** *** *** *** *** *** *** *** *** *** *** *** 1) RELEASE NOTES: --- --- ---- The release notes are now provided in PDF format in the file: \SOFTWARE\uCOS-II\DOC\RelV251.PDF 2) FEATURES SINCE V2.00: --- --- --- ----- All the features added since V2.00 are described in the PDF file: \SOFTWARE\uCOS-II\DOC\NewV251.PDF 3) EVENT FLAGS: -------------- Event Flags are discussed in AN-1007 (see www.Micrium.com/app_notes.htm) 4) QUICK REFERENCE CHART: ------------------------ A Quick Reference Chart for all the functions in V2.51 is provided in the following .PDF files: \SOFTWARE\uCOS-II\DOC\QuickRefChartV251-Color.PDF Once printed, simply FOLD the page in half and if you have a LAMINATION machine, you can protect the chart by laminating it.
上傳時間： 2015-04-06
上傳用戶：zq70996813
NORTi3 is a realtime multitasking operating system conforming to the micro-ITRON 3.0 specification. NORTi3 is divided into two packages: NORTi3 Standard and NORTi3 Extended. The product NORTi3 Extended has implemented all the system calls of level E placed as "added and extended functions” in the micro-ITRON specification as well as the system calls equivalent to level X.
標簽： specification multitasking micro-ITRON conforming
上傳時間： 2014-01-14
上傳用戶：saharawalker
