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Atmel AVR 單片機上網方案
The AVR Embedded Internet Toolkit is the fastest way to connect anyembedded design to the Internet. It includes an ATmega AVR microcontroller,dedicated hardware, and all required software protocols forconnecting to the Internet. The AVR Embedded Internet Toolkit is thefastest choice for getting started with embedded Internet and for developinga complete embedded application connected to the Internet.
標簽：
Atmel
AVR
單片機
方案
上傳時間：
2013-11-06
上傳用戶：xjz632
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Stellaris(群星)單片機的片上FLASH編程(英)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH LUMINARY MICRO PRODUCTS. NO LICENSE,EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO any INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THISDOCUMENT. EXCEPT AS PROVIDED IN LUMINARY MICRO’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS,LUMINARY MICRO ASSUMES NO LIABILITY WHATSOEVER, AND LUMINARY MICRO DISCLAIMS any EXPRESS OR IMPLIEDWARRANTY, RELATING TO SALE AND/OR USE OF LUMINARY MICRO’S PRODUCTS INCLUDING LIABILITY OR WARRANTIESRELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF any PATENT, COPYRIGHTOR OTHER INTELLECTUAL PROPERTY RIGHT. LUMINARY MICRO’S PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL,LIFE SAVING, OR LIFE-SUSTAINING APPLICATIONS.
標簽：
Stellaris
FLASH
單片機
編程
上傳時間：
2013-10-22
上傳用戶：JamesB
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Stellaris(群星)單片機加上32KB串行SRAM(英)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH LUMINARY MICRO PRODUCTS. NO LICENSE,EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO any INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THISDOCUMENT. EXCEPT AS PROVIDED IN LUMINARY MICRO’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS,LUMINARY MICRO ASSUMES NO LIABILITY WHATSOEVER, AND LUMINARY MICRO DISCLAIMS any EXPRESS OR IMPLIEDWARRANTY, RELATING TO SALE AND/OR USE OF LUMINARY MICRO’S PRODUCTS INCLUDING LIABILITY OR WARRANTIESRELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF any PATENT, COPYRIGHTOR OTHER INTELLECTUAL PROPERTY RIGHT. LUMINARY MICRO’S PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL,LIFE SAVING, OR LIFE-SUSTAINING APPLICATIONS.
標簽：
Stellaris
SRAM
32
KB
上傳時間：
2013-11-22
上傳用戶：lixqiang
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The CAT25128 is a 128−Kb Serial CMOS EEPROM device internally organized as 16Kx8 bits. This features a 64−byte page write buffer and supports the Serial Peripheral Interface (SPI) protocol. The device is enabled through a Chip Select (CS) input. In addition, the required bus signals are clock input (SCK), data input (SI) and data output (SO) lines. The HOLD input may be used to pause any serial communication with the CAT25128 device. The device featuressoftware and hardware write protection, including partial as well as full array protection.
標簽：
25128
EEPRO
CMOS
CAT
上傳時間：
2013-11-15
上傳用戶：fklinran
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Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their productsor to discontinue any product or service without notice, and advise customers to obtain the latestversion of relevant information to verify, before placing orders, that information being relied onis current and complete. All products are sold subject to the terms and conditions of sale suppliedat the time of order acknowledgement, including those pertaining to warranty, patentinfringement, and limitation of liability.
標簽：
Assembly
Language
C6000
320C
上傳時間：
2013-11-12
上傳用戶：chens000
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The PCA9516 is a BiCMOS integrated circuit intended forapplication in I2C and SMBus systems.While retaining all the operating modes and features of the I2Csystem, it permits extension of the I2C-bus by buffering both the data(SDA) and the clock (SCL) lines, thus enabling five buses of 400 pF.The I2C-bus capacitance limit of 400 pF restricts the number ofdevices and bus length. Using the PCA9516 enables the systemdesigner to divide the bus into five segments off of a hub where anysegment to segment transition sees only one repeater delay.
標簽：
5channel
9516
PCA
I2C
上傳時間：
2013-11-21
上傳用戶：q123321
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The PCA9541 is a 2-to-1 I2C-bus master selector designed for high reliability dual masterI2C-bus applications where system operation is required, even when one master fails orthe controller card is removed for maintenance. The two masters (for example, primaryand back-up) are located on separate I2C-buses that connect to the same downstreamI2C-bus slave devices. I2C-bus commands are sent by either I2C-bus master and are usedto select one master at a time. Either master at any time can gain control of the slavedevices if the other master is disabled or removed from the system. The failed master isisolated from the system and will not affect communication between the on-line masterand the slave devices on the downstream I2C-bus.
標簽：
master
C-bus
9541
PCA
上傳時間：
2013-10-09
上傳用戶：3294322651
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The PCA9544A provides 4 interrupt inputs, one for each channeland one open drain interrupt output. When an interrupt is generated byany device, it will be detected by the PCA9544A and the interruptoutput will be driven LOW. The channel need not be active fordetection of the interrupt. A bit is also set in the control byte.Bits 4 – 7 of the control byte correspond to channels 0 – 3 of thePCA9544A, respectively. Therefore, if an interrupt is generated byany device connected to channel 2, the state of the interrupt inputs isloaded into the control register when a read is accomplished.Likewise, an interrupt on any device connected to channel 0 wouldcause bit 4 of the control register to be set on the read. The mastercan then address the PCA9544A and read the contents of thecontrol byte to determine which channel contains the devicegenerating the interrupt. The master can then reconfigure thePCA9544A to select this channel, and locate the device generatingthe interrupt and clear it. The interrupt clears when the deviceoriginating the interrupt clears.
標簽：
4channel
multiple
9544A
9544
上傳時間：
2014-12-28
上傳用戶：潛水的三貢
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The PCA9549 provides eight bits of high speed TTL-compatible bus switching controlledby the I2C-bus. The low ON-state resistance of the switch allows connections to be madewith minimal propagation delay. any individual A to B channel or combination of channelscan be selected via the I2C-bus, determined by the contents of the programmable Controlregister. When the I2C-bus bit is HIGH (logic 1), the switch is on and data can flow fromPort A to Port B, or vice versa. When the I2C-bus bit is LOW (logic 0), the switch is open,creating a high-impedance state between the two ports, which stops the data flow.An active LOW reset input (RESET) allows the PCA9549 to recover from a situationwhere the I2C-bus is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C-busstate machine and causes all the bits to be open, as does the internal power-on resetfunction.
標簽：
switch
Octal
9549
with
上傳時間：
2014-11-22
上傳用戶：xcy122677
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The PCA9546A is a quad bidirectional translating switch controlled via the I2C-bus. TheSCL/SDA upstream pair fans out to four downstream pairs, or channels. any individualSCx/SDx channel or combination of channels can be selected, determined by thecontents of the programmable control register.
標簽：
channel
9546A
9546
PCA
上傳時間：
2013-11-16
上傳用戶：cc1915
