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archItecture

Nios II軟件開發人員手冊中的緩存和緊耦合存儲器部分

Nios II 軟件開發人員手冊中的緩存和緊耦合存儲器部分 Nios® II embedded processor cores can contain instruction and data caches. This chapter discusses cache-related issues that you need to consider to guarantee that your program executes correctly on the Nios II processor. Fortunately, most software based on the Nios II hardware abstraction layer (HAL) works correctly without any special accommodations for caches. However, some software must manage the cache directly. For code that needs direct control over the cache, the Nios II archItecture provides facilities to perform the following actions:

標簽： Nios 軟件開發存儲器

上傳時間： 2013-10-25

上傳用戶：蟲蟲蟲蟲蟲蟲
WP264-在數字視頻應用中使用CPLD

The CoolRunner-II CPLD is a highly uniform family of fast, low-power devices. Theunderlying archItecture is a traditional CPLD archItecture, combining macrocells intofunction blocks interconnected with a global routing matrix, the Xilinx AdvancedInterconnect Matrix (AIM). The function blocks use a PLA configuration that allowsall product terms to be routed and shared among any of the macrocells of the functionblock.

標簽： CPLD 264 WP 數字

上傳時間： 2013-11-03

上傳用戶：1037540470
WP312-Xilinx新一代28nm FPGA技術簡介

Xilinx Next Generation 28 nm FPGA Technology Overview Xilinx has chosen 28 nm high-κ metal gate (HKMG) highperformance,low-power process technology and combined it with a new unified ASMBL™ archItecture to create a new generation of FPGAs that offer lower power and higher performance. These devices enable unprecedented levels of integration and bandwidth and provide system architects and designers a fully programmable alternative to ASSPs and ASICs.

標簽： Xilinx FPGA 312 WP

上傳時間： 2013-12-07

上傳用戶：bruce
WP369可擴展式處理平臺-各種嵌入式系統的理想解決方案

WP369可擴展式處理平臺-各種嵌入式系統的理想解決方案：Delivering unrivaled levels of system performance,flexibility, scalability, and integration to developers,Xilinx's archItecture for a new Extensible Processing Platform is optimized for system power, cost, and size. Based on ARM's dual-core Cortex™-A9 MPCore processors and Xilinx’s 28 nm programmable logic,the Extensible Processing Platform takes a processor-centric approach by defining a comprehensive processor system implemented with standard design methods. This approach provides Software Developers a familiar programming environment within an optimized, full featured,powerful, yet low-cost, low-power processing platform.

標簽： 369 WP 擴展式處理平臺

上傳時間： 2013-10-18

上傳用戶：cursor
PLD對FPGA數據加密

SRAM-based FPGAs are non-volatile devices. Upon powerup, They are required to be programmed from an external source. This procedure allows anyone to easily monitor the bit-stream, and clone the device. The problem then becomes how can you effectively protect your intellectual property from others in an archItecture where the part is externally programmed?

標簽： FPGA PLD 數據加密

上傳時間： 2013-10-20

上傳用戶：磊子226
基于FPGA+DSP模式的智能相機設計

針對嵌入式機器視覺系統向獨立化、智能化發展的要求，介紹了一種嵌入式視覺系統--智能相機。基于對智能相機體系結構、組成模塊和圖像采集、傳輸和處理技術的分析，對國內外的幾款智能相機進行比較。綜合技術發展現狀，提出基于FPGA+DSP模式的硬件平臺，并提出智能相機的發展方向。分析結果表明，該系統設計可以實現脫離PC運行，完成圖像獲取與分析，并作出相應輸出。 Abstract: This paper introduced an embedded vision system-intelligent camera ，which was for embedded machine vision systems to an independent and intelligent development requirements. Intelligent camera archItecture， component modules and image acquisition， transmission and processing technology were analyzed. After comparing integrated technology development of several intelligent cameras at home and abroad， the paper proposed the hardware platform based on FPGA+DSP models and made clear direction of development of intelligent cameras. On the analysis of the design， the results indicate that the system can run from the PC independently to complete the image acquisition and analysis and give a corresponding output.

標簽： FPGA DSP 模式智能相機

上傳時間： 2013-11-14

上傳用戶：無聊來刷下
ref sdr sdram vhdl代碼

ref-sdr-sdram-vhdl代碼 SDR SDRAM Controller v1.1 readme.txt This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1. The PLL is targeted at APEX(TM) devices. Please regenerate for your chosen archItecture. Last updated September, 2002 Copyright ?2002 Altera Corporation. All rights reserved.

標簽： sdram vhdl ref sdr

上傳時間： 2013-10-23

上傳用戶：半熟1994
ISA(PC104)總線規范

ISA總線概述　　ISA總線: (Industry Standard archItecture:工業標準體系結構）是IBM公司為PC/AT電腦而制定的總線標準，為16位體系結構，只能支持16位的I/O設備，數據傳輸率大約是16MB/S。也稱為AT標準。開始時PC機面向個人及辦公室，定義了8位的ISA總線結構，對外公開，成為標準（ISO ISA標準）。第三方開發出許多ISA擴充板卡，推動了PC機的發展。1984年推出IBM-PC/AT系統，ISA從8位擴充到16位，地址線從20條擴充到24條。1988年，康柏、HP、NEC等9個廠商協同把ISA擴展到32位，即EISA總線(Extended ISA)。

標簽： ISA 104 PC 總線規范

上傳時間： 2013-10-16

上傳用戶：dajin
XMDS is a code generator that integrates equations. You write them down in human readable form in a

XMDS is a code generator that integrates equations. You write them down in human readable form in a XML file, and it goes away and writes and compiles a C++ program that integrates those equations as fast as it can possibly be done in your archItecture.

標簽： integrates generator equations readable

上傳時間： 2014-11-27

上傳用戶：hebmuljb
ava加密擴展即Java Cryptography Extension

ava加密擴展即Java Cryptography Extension，簡稱JCE。它是Sun的加密服務軟件，包含了加密和密匙生成功能。JCE是JCA（Java Cryptography archItecture）的一種擴展。 JCE沒有規定具體的加密算法，但提供了一個框架，加密算法的具體實現可以作為服務提供者加入。除了JCE框架之外，JCE軟件包還包含了SunJCE服務提供者，其中包括許多有用的加密算法，比如DES（Data Encryption Standard）和Blowfish。為簡單計，在本文中我們將用DES算法加密和解密字節碼。下面是用JCE加密和解密數據必須遵循的基本步驟：步驟1：生成一個安全密匙。在加密或解密任何數據之前需要有一個密匙。密匙是隨同被加密的應用一起發布的一小段數據，Listing 3顯示了如何生成一個密匙。【Listing 3：生成一個密匙】

標簽： Cryptography Extension Java ava

上傳時間： 2015-03-26

上傳用戶：nanxia