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This application note is intended for system designers who require a hardware implementation overview of the development board features such as the power supply, the clock management, the reset control, the boot mode settings and the debug management. It shows how to use the High-density and Medium-density STM32F10xxx product families and describes the minimum hardware resources required to develop an STM32F10xxx application.
上傳時間： 2013-04-24
上傳用戶：epson850
開關(guān)電源測試規(guī)范 說明 as
標(biāo)簽： 開關(guān)電源 測試規(guī)范
上傳時間： 2013-05-22
上傳用戶：小鵬
采用CPLD來培植ALTERA公司的CYCLONE系列FPGA，（AS，PS，F(xiàn)AS）可選
標(biāo)簽： CYCLONE ALTERA CPLD FPGA
上傳時間： 2013-08-27
上傳用戶：it男一枚
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
標(biāo)簽： Modelling Guide Navy VHDL
上傳時間： 2014-12-23
上傳用戶：xinhaoshan2016
We would like to welcome you as a user of the Allegro CX, a rugged, handheld fi eld PC for data collection. Developed with the input of data collection professionals worldwide, the Allegro CX is adaptable and versatile for use in a wide variety of data collection environments. The Allegro CX continues to utilize our ergonomic, lightweight design that is standard in our line of Allegro Field PCs. This design makes your Allegro easy to use for extended periods while moving to and from data collection sites in the fi eld.
標(biāo)簽： allegro manual cx 教程
上傳時間： 2014-12-23
上傳用戶：gaojiao1999
本文簡單討論并總結(jié)了VHDL、Verilog，System verilog 這三中語言的各自特點和區(qū)別As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.
標(biāo)簽： Verilog verilog System VHDL
上傳時間： 2013-10-16
上傳用戶：牛布牛
Abstract: This document explains how the Cupertino (MAXREFDES5#) subsystem reference design meets the higher resolution, higher voltage,and isolation needs of industrial control and industrial automation applications. Hardware and firmware design files as well as FFTs andhistograms from lab measurements are provided.
上傳時間： 2013-10-21
上傳用戶：mnacyf
Abstract: Many digital devices incorporate analog circuits. For instance, microprocessors, applicationspecificintegrated circuits (ASICs), and field-programmable gate arrays (FPGAs) may have internalvoltage references, analog-to-digital converters (ADCs) or digital-to-analog converters (DACs). However,there are challenges when you integrate more analog onto a digital design. As with all things in life, inelectronics we must always trade one parameter for another, with the application dictating the propertrade-off of analog function. In this application note, we examine how the demand for economy of spaceand cost pushes analog circuits onto digital substrates, and what design challenges emerge.
標(biāo)簽： 模擬IC 性能 模擬 數(shù)字化設(shè)計
上傳時間： 2013-11-17
上傳用戶：菁菁聆聽
Abstract: This application note describes the essential workings of an electrocardiogram (ECG). It discussesfactors that disrupt the ECG signals and make reliable, highly-accurate electrical characterization difficult. Theindustry-standard solution for ECG electrical characterization, which uses an analog front-end and ADCcombination, is explained. The article then introduces the MAX11040 simultaneous-sampling, sigma-deltaADC as a compelling, highly integrated solution that eliminates the need for the AFE, and saves both spaceand cost for the application.
標(biāo)簽： ADC 24位 心電圖 中的應(yīng)用
上傳時間： 2013-12-23
上傳用戶：sssl
The MAX2870 ultra-wideband phase-locked loop (PLL) and voltagecontrol oscillator (VCO) can operate in both integer-N and fractional-Nmodes, similar to the Analog Devices ADF4350 wideband synthesizer.This application note compares the MAX2870 and ADF4350 registers andloop filter design in detail. Users who already familiar with ADF4350 canuse this application note as a quick design reference.
標(biāo)簽： 寄存器 環(huán)路濾波器
上傳時間： 2014-12-23
上傳用戶：變形金剛
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