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base-v

  • // -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial //

    // -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined

    標簽: Description Behavorial wb_master Filename

    上傳時間: 2014-07-11

    上傳用戶:zhanditian

  • robocup 2D防真base平臺 是運行/開發防真機器人的必備平臺

    robocup 2D防真base平臺 是運行/開發防真機器人的必備平臺

    標簽: robocup base 運行 機器人

    上傳時間: 2016-10-17

    上傳用戶:13160677563

  • Because of the poor observability of Inertial Navigation System on stationary base, the estimation

    Because of the poor observability of Inertial Navigation System on stationary base, the estimation error of the azimuth will converge very slowly in initial alignment by means of Kalmari filtering, and making the time initial alignment is longer. In this paper, a fast estimation method of the azimuth error is creatively proposed for the initial alignment of INS on stationary base. On the basis of the the fast convergence of the leveling error, the azimuth error can be directly calculated. By means of this fast initial alignment method, the time of initial alignment is reduced greatly. The computer simulation results illustrate the efficiency of the method.

    標簽: observability Navigation estimation stationary

    上傳時間: 2014-01-03

    上傳用戶:wuyuying

  • This diskette (version 1.0) contains demonstration programs and source codes in MATLAB (v.5.2) for a

    This diskette (version 1.0) contains demonstration programs and source codes in MATLAB (v.5.2) for algorithms listed in the textbook Global Positioning Systems, Inertial Navigation, and Integration, by M. S. Grewal, Lawrence Weill, and A. P. Andrews, published by John Wiley and Sons, 2000. Contents: MATLAB (Version 5.2) Demonstrations & Scripts Chapter4 ephemeris.m calculates the GPS satellite position in ECEF coordinates from its ephemeris parameters. Chapter5 Klobuchar_fix.m calculates the ionospheric delay. Chapter6 (shows the quaternion utilities)

    標簽: demonstration diskette contains programs

    上傳時間: 2016-10-20

    上傳用戶:壞天使kk

  • 個人所得稅計算器 v個人所得稅計算器

    個人所得稅計算器 v個人所得稅計算器

    標簽: 計算器

    上傳時間: 2014-01-23

    上傳用戶:bibirnovis

  • Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH

    Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.

    標簽: SHIFTER name module Input

    上傳時間: 2013-12-13

    上傳用戶:himbly

  • Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH

    Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.

    標簽: SHIFTER name module Input

    上傳時間: 2014-01-20

    上傳用戶:三人用菜

  • 代碼分為兩部分:ff_const_mul.v和ff_mul.v

    代碼分為兩部分:ff_const_mul.v和ff_mul.v,從而實現GF乘法器,VERILOG編寫

    標簽: ff_const_mul ff_mul 代碼

    上傳時間: 2016-11-13

    上傳用戶:

  • 牛頓迭代法 若高階非線性方程組: u ( x , y) = 0 v ( x , y) = 0 可以用迭代公式

    牛頓迭代法 若高階非線性方程組: u ( x , y) = 0 v ( x , y) = 0 可以用迭代公式

    標簽: 牛頓 方程 迭代法 迭代

    上傳時間: 2014-02-10

    上傳用戶:wl9454

  • ram_dp_ar_aw.v 應該蠻有用的

    ram_dp_ar_aw.v 應該蠻有用的

    標簽: ram_dp_ar_aw

    上傳時間: 2013-12-03

    上傳用戶:cxl274287265

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