This paper shows the development of a 1024-point
radix-4 FFT VHDL core for applications in hardware signal processing, targeting low-cost FPGA technologies. The developed core is targeted into a Xilinx廬 Spartan鈩?3 XC3S200 FPGA with the inclusion of a VGA display interface and an external 16-bit data acquisition system for performance evaluation purposes. Several tests were performed in order to verify FFT core functionality, besides the time performance analysis highlights the core advantages over commercially available DSPs and Pentium-based PCs. The core is compared with similar third party IP cores targeting resourceful FPGA technologies. The novelty of this work is to provide a lowcost, resource efficient core for spectrum analysis
applications.
Embedded System Design using 8031 microcontroller defines many steps in development of embedded systems using the most popular 8-bit microcontroller using various examples. I hope this would be useful to everyone.
200-MHz ARM920T Processor
• 16-kbyte Instruction Cache
• 16-kbyte Data Cache
• Linux® , Microsoft® Windows® CE-enabled MMU
• 100-MHz System Bus
• MaverickCrunch™ Math Engine
• Floating Point, Integer, and Signal Processing
Instructions
• Optimized for digital music compression and
decompression algorithms.
• Hardware interlocks allow in-line coding.
• MaverickKey™ IDs
• 32-bit Unique ID can be used for DRM-compliant
128-bit random ID.
• Integrated Peripheral Interfaces
• 32-bit SDRAM Interface
使用FPGA/CPLD設置語音AD、DA轉換芯片AIC23，FPGA/CPLD系統時鐘為24.576MHz
1、AIC系統時鐘為12.288MHz，SPI時鐘為6.144MHz
2、AIC處于主控模式
3、input bit length 16bit output bit length 16bit MSB first
4、幀同步在96KHz
Here are the functions for Hamming code 7.4 and Extended Hamming code 8.4
encoding and decoding.
For 7.4 code, one error per 7-bit codeword can be corrected.
For 8.4 code, one error per 8-bit codeword can be corrected
and not less than 2 errors can be detected.
A combined space鈥搕ime block coding (STBC) and eigen-space tracking
(EST) scheme in multiple-input-multiple-output systems is
proposed. It is proved that the STBC-EST is capable of shifting
hardware complexity from the receiver to the transmitter without
any bit error rate (BER) performance loss. A computation efficient
EST algorithm is also proposed, which makes the STBC-EST affordable.
Simulation results show that the STBC-EST with a modest
feedback requirement results in a negligible BER performance loss
compared with a dual system configuration.
SCSI Multimedia Commands 鈥?2 (MMC-2)
NCITS 333 T10/1228-D
4.1.1. CD address reporting formats (MSF bit)
Several CD commands can report addresses either in logical block address or in MSF format (see Table 1).
The READ HEADER, READ SUB-CHANNEL, and READ TOC/PMA/ATIP commands have this Feature
USBHostSlave is a USB 1.1 host and Device IP core.
– Supports full speed (12Mbps) and low speed (1.5Mbps) operation.
– USB Device has four endpoints, each with their own independent FIFO.
– Supports the four types of USB data transfer control, bulk, interrupt, and isochronous
transfers.
– Host can automatically generate SOF packets.
– 8-bit Wishbone slave bus interface.
– FIFO depth configurable via paramters.
This program implements a PIC-based fuzzy inference engine for the Fudge fuzzy development system from Motorola.
It works by taking the output from Fudge for the 68HC11 processor, and converting it to a MPASM compatible assembler file using the convert
batch file.
This file can then be incorporated with fuzzy.asm to create a fuzzy inference engine.
Tool chain
----------
FUDGE -> Fuzzy Rules -> MC68HC11.ASM -> CONVERT.BAT -> RULES.ASM
-> MPASM FUZZY.ASM -> INTEL HEX
Fuzzy input registers
---------------------
current_ins 1..8 x 8-bit raw inputs
Fuzzy inference function
------------------------
FuzzyEngine
Fuzzy output registers
----------------------
cog_outs 1..8 x 8-bit raw outputs
