// -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined
標(biāo)簽： Description Behavorial wb_master Filename
上傳時(shí)間： 2014-07-11
上傳用戶：zhanditian
The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general control and data transfer communication between ICs. Some of the features of the I2C bus are: • Two signal lines, a serial data line (SDA) and a serial clock line (SCL), and ground are required. A 12V supply line (500mA max.) for powering the peripherals often may be present. • Each device connected to the bus is software addressable by a unique address and simple master/ slave relationships exist at all times masters can operate as master-transmitters or as master-receivers. • The I2C bus is a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer systems. • Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 Kbit/s in the standard mode or up to 400 Kbit/s in the fast mode.
標(biāo)簽： bus bidirectional primarily designed
上傳時(shí)間： 2013-12-11
上傳用戶：jeffery
iic總線控制器VHDL實(shí)現(xiàn) -- VHDL Source Files: i2c.vhd -- top level file i2c_control.vhd -- control function for the I2C master/slave shift.vhd -- shift register uc_interface.vhd -- uC interface function for an 8-bit 68000-like uC upcnt4.vhd -- 4-bit up counter i2c_timesim.vhd -- post-route I2C simulation netlist
標(biāo)簽： VHDL c_control vhd control
上傳時(shí)間： 2016-10-30
上傳用戶：woshiayin
WLAN仿真－發(fā)送機(jī) wlan No Comments 設(shè)置完系統(tǒng)參數(shù)后，開始產(chǎn)生發(fā)送數(shù)據(jù)。 1. 產(chǎn)生隨機(jī)的發(fā)送bit（tx_bits），這里不考慮信道編碼。 2. QAM映射 3. 將數(shù)據(jù)映射到不同載波，形成OFDM符號(hào) 4. 產(chǎn)生pilot，并將pilot插入OFDM符號(hào)中 5. 加入dc和guard子載波 6. 進(jìn)行ifft，將頻域信號(hào)變到時(shí)域，并加入循環(huán)前綴 7. 對(duì)信號(hào)進(jìn)行overlap window 8. 在時(shí)域產(chǎn)生short preamble 9. 在時(shí)域產(chǎn)生long preamble 10. 將preamble和數(shù)據(jù)符號(hào)組成packet 11. 升采樣 得到信道傳輸?shù)臄?shù)據(jù)Tx_signal_up 具體程序見附件 wlan_transmitter.m
標(biāo)簽： Comments WLAN wlan No
上傳時(shí)間： 2016-11-09
上傳用戶：exxxds
16點(diǎn)FFT VHDL源程序，The xFFT16 fast Fourier transform (FFT) Core computes a 16-point complex FFT. The input data is a vector of 16 complex values represented as 16-bit 2’s complement numbers – 16-bits for each of the real and imaginary component of a datum.
上傳時(shí)間： 2013-12-20
上傳用戶：yph853211
The MIPS32® 4KEm™ core from MIPS® Technologies is a member of the MIPS32 4KE™ processor core family. It is a high-performance, low-power, 32-bit MIPS RISC core designed for custom system-on-silicon applications. The core is designed for semiconductor manufacturing companies, ASIC developers, and system OEMs who want to rapidly integrate their own custom logic and peripherals with a high-performance RISC processor. It is highly portable across processes, and can be easily integrated into full system-on-silicon designs, allowing developers to focus their attention on end-user products. The 4KEm core is ideally positioned to support new products for emerging segments of the digital consumer, network, systems, and information management markets, enabling new tailored solutions for embedded applications.
標(biāo)簽： MIPS 8482 Technologies 174
上傳時(shí)間： 2014-12-22
上傳用戶：semi1981
VHDL語言實(shí)現(xiàn)的穿行通訊，可實(shí)現(xiàn)閉環(huán)操作，通訊過程中每個(gè)bit位采樣3次，保證數(shù)據(jù)準(zhǔn)確。
上傳時(shí)間： 2014-01-13
上傳用戶：ynsnjs
DDR SDRAM控制器的VHDL源代碼，含詳細(xì)設(shè)計(jì)文檔。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.
上傳時(shí)間： 2014-11-01
上傳用戶：l254587896
軟件簡(jiǎn)介：HI-TECH PICC 是一款高效的C編譯器，支持Microchip PICmicro 10/12/14/16/17系列控制器。是一款強(qiáng)勁的標(biāo)準(zhǔn)C編譯器，完全遵守ISO/ANSI C，支持所有的數(shù)據(jù)類型包括24 and 32 bit IEEE 標(biāo)準(zhǔn)浮點(diǎn)類型。智能優(yōu)化產(chǎn)生高質(zhì)量的代碼。屬于第三方開發(fā)工具。能和MPLAB整合，內(nèi)嵌開發(fā)環(huán)境（HI－TIDE）。 Hi-tech PICC Compiler v8.注冊(cè)碼 Serial: HCPIC-88888 First Name: ONE Last Name: TWO Company Name:ONE TWO Registration: 任意填，但一定要填 Activation: NPCBACMJKLPCADKLOEDBFPIOCIBAEIDI
標(biāo)簽： HI-TECH PICC 軟件 C編譯器
上傳時(shí)間： 2016-12-16
上傳用戶：Andy123456
H.264/AVC, the result of the collaboration between the ISO/IEC Moving Picture Experts Group and the ITU-T Video Coding Experts Group, is the latest standard for video coding. The goals of this standardization effort were enhanced compression efficiency, network friendly video representation for interactive (video telephony) and non-interactive applications (broadcast, streaming, storage, video on demand). H.264/AVC provides gains in compression efficiency of up to 50％ over a wide range of bit rates and video resolutions compared to previous standards. Compared to previous standards, the decoder complexity is about four times that of MPEG-2 and two times that of MPEG-4 Visual Simple Profile. This paper provides an overview of the new tools, features and complexity of H.264/AVC.
標(biāo)簽： the collaboration between Experts
上傳時(shí)間： 2013-12-30
上傳用戶：dongbaobao
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