Wishbone to LPC (Low-Pin Count) bridge, includes master and slave modules. Supports 8-bit I/O Read and Write cycles, 8-bit Memory Read/Write cycles, DMA cycles, and up to 32-bit Firmware memory read/write cycles. Serial IRQ support is also provided.
None of this has been tested (yet) with a third-party LPC Peripheral or Host.
This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.
userial is an Free project building an USB to I2C/SPI/GPIO bridge, using the Atmel AT90USB647 chip. Hardware and Software are released under an Open Source licence. It supports the following interfaces:
* USB interface (serial emulation)
* JTAG
* I2C (TWI)
* SPI
* 8 General purpose digital I/O
* 4 Analog to Digital converters (currently no firmware support)
近些年來，隨著電力電子技術的發展，電力電子系統集成受到越來越多的關注，其中標準化模塊的串并聯技術成為研究熱點之一。輸入并聯輸出串聯型(Input-Parallel and Output-Series，IPOS)組合變換器適用于大功率高輸出電壓的場合。 要保證IPOS組合變換器正常工作，必須保證其各模塊的輸出電壓均衡。本文首先揭示了IPOS組合變換器中每個模塊輸入電流均分和輸出電壓均分之間的關系，在此基礎上提出一種輸出均壓控制方案，該方案對系統輸出電壓調節沒有影響。選擇移相控制全橋(Full-bridge，FB)變換器作為基本模塊，對n個全橋模塊組成的IPOS組合變換器建立小信號數學模型，推導出采用輸出均壓控制方案的IPOS-FB系統的數學模型，該模型證明各模塊輸出均壓閉環不影響系統輸出電壓閉環的調節，給出了模塊輸出均壓閉環和系統輸出電壓閉環的補償網絡參數設計。對于IPOS組合變換器，采用交錯控制，由于電流紋波抵消效應，輸入濾波電容容量可大大減小；由于電壓紋波抵消作用，在相同的系統輸出電壓紋波下，各模塊的輸出濾波電容可大大減小，由此可以提高變換器的功率密度。 根據所提出的輸出均壓控制策略，在實驗室研制了一臺由兩個1kW全橋模塊組成的IPOS-FB原理樣機，每個模塊輸入電壓為270V，輸出電壓為180V。并進行了仿真和實驗驗證，結果均表明本控制方案是正確有效的。
