■ High Performance, Low Power AVR? 8-Bit Microcontroller ■ Advanced RISC Architecture –120 Powerful Instructions – Most Single cLock Cycle Execution –32 x 8 General Purpose Working Registers –Fully Static Operation
標(biāo)簽： Atmel
上傳時間： 2013-06-01
上傳用戶：tccc
比例-積分-微分（PID）是過程控制中最常用的一種控制算法。算法簡單而且容易理解，應(yīng)用十分廣泛。但由于應(yīng)用領(lǐng)域的不同，功能上差別很大，系統(tǒng)的控制要求及關(guān)心的控制對象也不相同。數(shù)字PID控制比連續(xù)PID控制更為優(yōu)越，因為計算機(jī)程序的靈活性，很容易克服連續(xù)PID控制中存在的問題，經(jīng)修正而得到更完善的數(shù)字PID算法。本文以三相全控整流橋阻性負(fù)載為實際電路，控制主電路電壓，旨在提出一種智能數(shù)字PID控制系統(tǒng)的設(shè)計思路，并給出了詳細(xì)的硬件設(shè)計及初步軟件設(shè)計思路。 PID控制系統(tǒng)采用高性能、低功耗的ARM微處理器S3C44BO作為核心處理單元，內(nèi)部的10位ADC作為信號采集模塊，采用了矩陣鍵盤和640*480的液晶作為人機(jī)接口；串口作為通信模塊實現(xiàn)了上位機(jī)的監(jiān)控。采用芯片內(nèi)部自帶的PWM模塊，輸出16M Hz PWM信號并經(jīng)過一階低通濾波器得到0～5V的控制信號用于觸發(fā)主電路控制器，實現(xiàn)PID整定。 軟件方面，分析和研究了uC/OSⅡ的內(nèi)核源碼，實現(xiàn)了其在32位微處理器上的移植，作為管理各個子程序執(zhí)行的系統(tǒng)軟件。選用了圖形處理軟件uC/GUI用于完成LCD顯示及控制。PID算法采用了增量式數(shù)字PID算法，采用規(guī)一化算法進(jìn)行參數(shù)選取。上位機(jī)部分采用了C＃語言進(jìn)行編寫。另外，采用了RTC（Real Time cLock）作為系統(tǒng)時鐘，可以實現(xiàn)系統(tǒng)的定時運行、定時模式切換等。在上位機(jī)上也可以方便的控制程序的執(zhí)行，實現(xiàn)遠(yuǎn)程監(jiān)控。 在論文的最后詳細(xì)的介紹了智能PID控制系統(tǒng)在三相全控橋主電路中的具體應(yīng)用。總結(jié)了調(diào)試中遇到的問題，對今后工作中需要進(jìn)一步改善和探索的地方進(jìn)行了展望。
標(biāo)簽： ARM PID 控制系統(tǒng)
上傳時間： 2013-08-01
上傳用戶：lvzhr
BGA布線指南 BGA CHIP PLACEMENT AND ROUTING RULE BGA是PCB上常用的組件，通常CPU、NORTH BRIDGE、SOUTH BRIDGE、AGP CHIP、CARD BUS CHIP…等，大多是以bga的型式包裝，簡言之，80﹪的高頻信號及特殊信號將會由這類型的package內(nèi)拉出。因此，如何處理BGA package的走線，對重要信號會有很大的影響。 通常環(huán)繞在BGA附近的小零件，依重要性為優(yōu)先級可分為幾類： 1. by pass。 2. cLock終端RC電路。 3. damping（以串接電阻、排組型式出現(xiàn)；例如memory BUS信號） 4. EMI RC電路（以dampin、C、pull height型式出現(xiàn)；例如USB信號）。 5. 其它特殊電路（依不同的CHIP所加的特殊電路；例如CPU的感溫電路）。 6. 40mil以下小電源電路組（以C、L、R等型式出現(xiàn)；此種電路常出現(xiàn)在AGP CHIP or含AGP功能之CHIP附近，透過R、L分隔出不同的電源組）。 7. pull low R、C。 8. 一般小電路組（以R、C、Q、U等型式出現(xiàn)；無走線要求）。 9. pull height R、RP。 中文DOC，共5頁，圖文并茂
上傳時間： 2013-04-24
上傳用戶：cxy9698
This application note is intended for system designers who require a hardware implementation overview of the development board features such as the power supply, the cLock management, the reset control, the boot mode settings and the debug management. It shows how to use the High-density and Medium-density STM32F10xxx product families and describes the minimum hardware resources required to develop an STM32F10xxx application.
上傳時間： 2013-04-24
上傳用戶：epson850
英文描述： Synchronous Up/Down Decade Counters(single cLock line) 中文描述： 同步向上/向下十年計數(shù)器（單時鐘線）
上傳時間： 2013-06-18
上傳用戶：haohaoxuexi
Abstract: This application note describes how sampling cLock jitter (time interval error or "TIE jitter") affectsthe performance of delta-sigma digital-to-analog converters (DACs). New insights explain the importanceof separately specifying low-frequency (< 2x passband frequency) and high-frequency or wideband (> 2xpassband frequency) jitter tolerance in these devices. The article also provides an application example ofa simple highly jittered cycle-skipped sampling cLock and describes a method for generating a properbroadband jittered cLock. The document then goes on to compare Maxim's audio DAC jitter tolerance tocompetitor audio DACs. Maxim's exceptionally high jitter tolerance allows very simple and low-cost samplecLock implementations.
標(biāo)簽： DAC 音頻 數(shù)模轉(zhuǎn)換器 抖動
上傳時間： 2013-10-25
上傳用戶：banyou
With more and more multi-frequency cLocks being used in today's chips, especially in the communications field, it is often necessary to switch the source of a cLock line while the chip is running.
上傳時間： 2013-10-10
上傳用戶：1214209695
Many applications require a cLock signal to be synchronous, phase-locked, or derived fromanother signal, such as a data signal or another cLock. This type of cLock circuit is important in
標(biāo)簽： XAPP DPLL 854 數(shù)字鎖相環(huán)
上傳時間： 2014-12-23
上傳用戶：qq21508895
Most circuit designers are familiar with diode dynamiccharacteristics such as charge storage, voltage dependentcapacitance and reverse recovery time. Less commonlyacknowledged and manufacturer specifi ed is diode forwardturn-on time. This parameter describes the timerequired for a diode to turn on and clamp at its forwardvoltage drop. Historically, this extremely short time, unitsof nanoseconds, has been so small that user and vendoralike have essentially ignored it. It is rarely discussed andalmost never specifi ed. Recently, switching regulator cLockrate and transition time have become faster, making diodeturn-on time a critical issue. Increased cLock rates aremandated to achieve smaller magnetics size; decreasedtransition times somewhat aid overall effi ciency but areprincipally needed to minimize IC heat rise. At cLock speedsbeyond about 1MHz, transition time losses are the primarysource of die heating.
標(biāo)簽： 二極管 導(dǎo)通 開關(guān)穩(wěn)壓器
上傳時間： 2013-10-10
上傳用戶：誰偷了我的麥兜
A complete design for a data acquisition card for the IBM PC is detailed in this application note. Additionally, C language code is provided to allow sampling of data at speed of more than 20kHz. The speed limitation is strictly based on the execution speed of the "C" data acquisition loop. A "Turbo" XT can acquire data at speeds greater than 20kHz. Machines with 80286 and 80386 processors can go faster than 20kHz. The computer that was used as a test bed in this application was an XT running at 4.77MHz and therefore all system timing and acquisition time measurements are based on a 4.77MHz cLock speed.
標(biāo)簽： 1099 LTC 數(shù)據(jù) 采集板
上傳時間： 2013-10-29
上傳用戶：BOBOniu
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