一、版權(quán)信息PCI-51XX系列智能CAN接口卡及相關(guān)軟件均屬廣州市周立功單片機發(fā)展有限公司所有，其產(chǎn)權(quán)受國家法律絕對保護，未經(jīng)本公司授權(quán)，其他公司、單位、代理商及個人不得非法使用和拷貝，否則將受到國家法律的嚴(yán)厲制裁。您若需要我公司產(chǎn)品及相關(guān)信息，請及時與我們聯(lián)系，我們將熱情接待。廣州周立功單片機發(fā)展有限公司保留在任何時候修訂本用戶手冊且不需通知的權(quán)利。 二、功能特點PCI-51XX智能CAN接口卡是具有PCI接口的高性能CAN總線通訊適配卡，它使PC機方便地連接到CAN總線上，實現(xiàn)CAN2.0B協(xié)議的數(shù)據(jù)通訊。PCI-51XX智能CAN接口卡采用標(biāo)準(zhǔn)PCI接口，實現(xiàn)與主機PC的高速數(shù)據(jù)交換。接口卡上自帶光電隔離模塊，使PC機避免由于地環(huán)流的損壞，增強系統(tǒng)在惡劣環(huán)境中使用的可靠性。PCI-51XX智能CAN接口卡配有可在Win98/Me、Win2000/XP下工作的驅(qū)動程序，使用通用CAN接口庫，使開發(fā)簡單化，并包含在VC++、C++Builder、Delphi、VB下開發(fā)的詳細(xì)應(yīng)用例程。
上傳時間： 2013-10-08
上傳用戶：wangyi39
ACPCI系列的產(chǎn)品就是專為工控機和臺式機及其他電腦工程項目和測試調(diào)試設(shè)計的。和計算機的連接接口是通用的PCI接口，ACPCI是南京來可電子根據(jù)多年的CAN總線工程應(yīng)用經(jīng)驗總結(jié)而成的，力求在CAN總線的兼容性、穩(wěn)定性和標(biāo)準(zhǔn)性上做到最好，ACPCI的單通道發(fā)送速度最高大于5000幀/秒，單通道接收速度最高大于7000幀/秒。總線2500V DC-DC隔離，總線接口防雷擊浪涌保護，配套有免費的測試軟件Adawin CANTest，方便對卡和客戶的CAN應(yīng)用系統(tǒng)進(jìn)行測試。
標(biāo)簽： DataSheet ACPCI 1.1 PCI
上傳時間： 2013-11-08
上傳用戶：born2007
BIOS emulator and interface to Realmode X86 Emulator Library Can emulate a PCI Graphic Controller VGA bios on a powerpc platform
標(biāo)簽： Controller interface emulator Realmode
上傳時間： 2015-11-02
上傳用戶：zjf3110
Peak-CAN控制器(PCI接口)的驅(qū)動程序，for linux，兼容SJA1000 CAN設(shè)備。
上傳時間： 2014-01-10
上傳用戶：lili123
完整的在Windows下 PCI CAN卡的驅(qū)動程序及測試程序
標(biāo)簽： Windows PCI CAN 驅(qū)動程序
上傳時間： 2013-12-23
上傳用戶：15736969615
一個關(guān)于PCI CAN開發(fā)板的windows下的驅(qū)動程序,用DDK做的,希望對做PCI CAN板的朋友有用
上傳時間： 2013-12-14
上傳用戶：lili123
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
標(biāo)簽： pci PCB 設(shè)計規(guī)范
上傳時間： 2013-10-15
上傳用戶：busterman
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
標(biāo)簽： pci PCB 設(shè)計規(guī)范
上傳時間： 2014-01-24
上傳用戶：s363994250
PCI Hot-Plug Specification Revision 1.0 The primary objective of this specification is to enable higher availability of file and application servers by standardizing key aspects of the process of removing and installing PCI adapter cards while the system is running. Although these same principles can be applied to desktop and portable systems using PCI buses, the operations described here target server platforms.
標(biāo)簽： Specification specification objective Hot-Plug
上傳時間： 2013-12-09
上傳用戶：zyt
PCI-to-PCI Bridge Architecture Specification Revision 1.1 This specification establishes the requirements that a PCI-to-PCI bridge must meet to be compliant to this specification and the PCI Local Bus Specification. In addition, the requirements for optional extensions are specified. This specification does not describe the implementation details of any particular requirement or optional feature of a PCI-to-PCI bridge, nor is it a goal of this specification to describe any particular PCI-to-PCI bridge implementation. However, some recommendations are provided for some implementation-specific features that can be provided by a PCI-to-PCI bridge.
標(biāo)簽： Specification specification Architecture establishes
上傳時間： 2014-01-14
上傳用戶：caiiicc
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