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Computational models are commonly used in engineering design and scientific discovery activities for simulating
complex physical systems in disciplines such as fluid mechanics, structural dynamics, heat transfer, nonlinear
structural mechanics, shock physics, and many others. These simulators can be an enormous aid to engineers who
want to develop an understanding and/or predictive capability for complex behaviors typically observed in the
corresponding physical systems. Simulators often serve as virtual prototypes, where a set of predefined system
parameters, such as size or location dimensions and material properties, are adjusted to improve the performance
of a system, as defined by one or more system performance objectives. Such optimization or tuning of the
virtual prototype requires executing the simulator, evaluating performance objective(s), and adjusting the system
parameters in an iterative, automated, and directed way. System performance objectives can be formulated, for
example, to minimize weight, cost, or defects; to limit a critical temperature, stress, or vibration response; or
to maximize performance, reliability, throughput, agility, or design robustness. In addition, one would often
like to design computer experiments, run parameter studies, or perform uncertainty quantification (UQ). These
approaches reveal how system performance changes as a design or uncertain input variable changes. Sampling
methods are often used in uncertainty quantification to calculate a distribution on system performance measures,
and to understand which uncertain inputs contribute most to the variance of the outputs.
A primary goal for Dakota development is to provide engineers and other disciplinary scientists with a systematic
and rapid means to obtain improved or optimal designs or understand sensitivity or uncertainty using simulationbased
models. These capabilities generally lead to improved designs and system performance in earlier design
stages, alleviating dependence on physical prototypes and testing, shortening design cycles, and reducing product
development costs. In addition to providing this practical environment for answering system performance questions,
the Dakota toolkit provides an extensible platform for the research and rapid prototyping of customized
methods and meta-algorithms
標簽：
Optimization and Uncertainty Quantification
上傳時間：
2016-04-08
上傳用戶：huhu123456
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The TAS3204 is a highly-integrated audio system-on-chip (SOC) consisting of a fully-programmable, 48-bit digital audio processor, a 3:1 stereo analog input MUX, four ADCs, four DACs, and other analog functionality. The TAS3204 is programmable with the graphical PurePath Studio? suite of DSP code development software. PurePath Studio is a highly intuitive, drag-and-drop environment that minimizes software development effort while allowing the end user to utilize the power and flexibility of the TAS3204’s digital audio processing core.
TAS3204 processing capability includes speaker equalization and crossover, volume/bass/treble control, signal mixing/MUXing/splitting, delay compensation, dynamic range compression, and many other basic audio functions. Audio functions such as matrix decoding, stereo widening, surround sound virtualization and psychoacoustic bass boost are also available with either third-party or TI royalty-free algorithms.
The TAS3204 contains a custom-designed, fully-programmable 135-MHz, 48-bit digital audio processor. A 76-bit accumulator ensures that the high precision necessary for quality digital audio is maintained during arithmetic operations.
Four differential 102 dB DNR ADCs and four differential 105 dB DNR DACs ensure that high quality audio is maintained through the whole signal chain as well as increasing robustness against noise sources such as TDMA interference.
The TAS3204 is composed of eight functional blocks:
Clocking System
Digital Audio Interface
Analog Audio Interface
Power supply
Clocks, digital PLL
I2C control interface
8051 MCUcontroller
Audio DSP – digital audio processing
特性
Digital Audio Processor
Fully Programmable With the Graphical, Drag-and-Drop PurePath Studio? Software Development Environment
135-MHz Operation
48-Bit Data Path With 76-Bit Accumulator
Hardware Single-Cycle Multiplier (28 × 48)
標簽：
3204
tas
上傳時間：
2016-05-06
上傳用戶：fagong
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The CommScope InstaPATCH? 360 and ReadyPATCH? solutions utilize a
standards-compliant multi-fiber connector to provide high density termination
capability. The connector is called an MPO (Multi-fiber Push On) connector by
the standards. In many cases, multi-fiber connector products are referred to as
MTP connectors. This document is intended to clarify the difference between the two terms – MPO and MTP.
標簽：
MPO
MTP
插件
定義
上傳時間：
2017-04-12
上傳用戶：asdfghjkl1234567890
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The 4.0 kbit/s speech codec described in this paper is based on a
Frequency Domain Interpolative (FDI) coding technique, which
belongs to the class of prototype waveform Interpolation (PWI)
coding techniques. The codec also has an integrated voice
activity detector (VAD) and a noise reduction capability. The
input signal is subjected to LPC analysis and the prediction
residual is separated into a slowly evolving waveform (SEW) and
a rapidly evolving waveform (REW) components. The SEW
magnitude component is quantized using a hierarchical
predictive vector quantization approach. The REW magnitude is
quantized using a gain and a sub-band based shape. SEW and
REW phases are derived at the decoder using a phase model,
based on a transmitted measure of voice periodicity. The spectral
(LSP) parameters are quantized using a combination of scalar
and vector quantizers. The 4.0 kbits/s coder has an algorithmic
delay of 60 ms and an estimated floating point complexity of
21.5 MIPS. The performance of this coder has been evaluated
using in-house MOS tests under various conditions such as
background noise. channel errors, self-tandem. and DTX mode
of operation, and has been shown to be statistically equivalent to
ITU-T (3.729 8 kbps codec across all conditions tested.
標簽：
frequency-domain
interpolation
performance
Design
kbit_s
speech
coder
based
and
of
上傳時間：
2018-04-08
上傳用戶：kilohorse
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DESCRIPTION
The Texas Instruments MSP430 family of ultra-low-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 μs.
The MSP430G2x13 and MSP430G2x53 series are ultra-low-power mixed signal microcontrollers with built-in 16-
bit timers, up to 24 I/O capacitive-touch enabled pins, a versatile analog comparator, and built-in communication
capability using the universal serial communication interface. In addition the MSP430G2x53 family members
have a 10-bit analog-to-digital (A/D) converter. For configuration details see Table 1.
Typical applications include low-cost sensor systems that capture analog signals, convert them to digital values,
and then process the data for display or for transmission to a host system.
標簽：
G2553
2553
430G
MSP
430
上傳時間：
2018-12-25
上傳用戶：ygyh
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High-Speed, Low-Power
Dual Operational Amplifier
The AD826 features high output current drive capability of
50 mA min per amp, and is able to drive unlimited capacitive
loads. With a low power supply current of 15 mA max for both
amplifiers, the AD826 is a true general purpose operational
amplifier.
The AD826 is ideal for power sensitive applications such as video
cameras and portable instrumentation. The AD826 can operate
from a single +5 V supply, while still achieving 25 MHz of band
width. Furthermore the AD826 is fully specified from a single
+5 V to ±15 V power supplies.
The AD826 excels as an ADC/DAC buffer or active filter in
data acquisition systems and achieves a settling time of 70 ns
to 0.01%, with a low input offset voltage of 2 mV max. The
AD826 is available in small 8-lead plastic mini-DIP and SO
packages.
標簽：
826
AD
上傳時間：
2020-04-19
上傳用戶：su1254
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The capability of radio waves to provide almost instantaneous distant communications
without interconnecting wires was a major factor in the explosive growth of communica-
tions during the 20th century. With the dawn of the 21st century, the future for communi-
cations systems seems limitless. The invention of the vacuum tube made radio a practical
and affordable communications medium.
標簽：
Communications
Receivers
上傳時間：
2020-05-26
上傳用戶：shancjb
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GaN is an already well implanted semiconductor
technology, widely diffused in the LED optoelectronics
industry. For about 10 years, GaN devices have also been
developed for RF wireless applications where they can
replace Silicon transistors in some selected systems. That
incursion in the RF field has open the door to the power
switching capability in the lower frequency range and
thus to the power electronic applications.
Compared to Silicon, GaN exhibits largely better figures
for most of the key specifications: Electric field, energy
gap, electron mobility and melting point. Intrinsically,
GaN could offer better performance than Silicon in
terms of: breakdown voltage, switching frequency and
Overall systems efficiency.
標簽：
GaN-on-Si
Displace
and
SiC
Si
上傳時間：
2020-06-07
上傳用戶：shancjb
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Wide 2.2V to 6V Input Voltage Range
? 0.20V FB adjustable LED drive current
? Directly drive 9 Series 1W LED at
VIN>=6V
? Fixed 800KHz Switching Frequency
? Max. 3A Switching Current capability
? Up to 92% efficiency
? Excellent line and load regulation
? EN PIN TTL shutdown capability
? Internal Optimize Power MOSFET
標簽：
sc3633
上傳時間：
2021-11-05
上傳用戶：d1997wayne
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The PW4055 is a complete constant-current /constant-voltage linear charger for single cell lithiumion batteries.Its ThinSOT package and low external component count make the PW4055 ideallysuited for portable applications.Furthermore, the PW4055 is specifically designed to work within USBpower specifications.The PW4055 No external sense resistor is needed, and no blocking diode is required due to theinternal MOSFET architecture.Thermal feedback regulates the charge current to limit the dietemperature during high power operation or high ambient temperature. The charge voltage is fixedat 4.2V, and the charge current can be programmed externally with a single resistor. The PW4055automatically terminates the charge cycle when the charge current drops to 1/10th the programmedvalue after the final float voltage is reached. When the input supply (wall adapter or USB supply) isremoved, the PW4055 automatically enters a low current state, dropping the battery drain currentto less than 2μA. The PW4055 can be put into shutdown mode, reducing the supply current to 25μA.The BAT pin has a 7KV ESD(HBM) capability. Other features include charge current monitor, undervoltage lockout, automatic recharge and a status pin to indicate charge termination and the presenceof an input voltage
標簽：
pw4055
上傳時間：
2022-02-11
上傳用戶：jason_vip1
