亚洲欧美第一页_禁久久精品乱码_粉嫩av一区二区三区免费野_久草精品视频

蟲蟲首頁| 資源下載| 資源專輯| 精品軟件
登錄| 注冊

chAnnel

  • Virtex-5 GTP Transceiver Wizar

    The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibrechAnnel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts

    標簽: Transceiver Virtex Wizar GTP

    上傳時間: 2013-10-23

    上傳用戶:leyesome

  • EDGE信道分配原則

      Contents   1 Introduction 1   2 Glosary 1   2.1 Concepts 1   2.2 Abbreviations and acronyms 4   3 Capabilities 6   4 Technical Description 6   4.1 General 6   4.2 Service oriented Allocation of Resources on the Abis   interface (SARA) 8   4.3 Configuration of dedicated PDCHs in Packet Switched   Domain (PSD) 10   4.4 Handling of Packet Data traffic 15   4.5 chAnnel selection in Cicuit Switched Domain (CSD) 19   4.6 Return of PDCHs to Cicuit Switched Domain (CSD) 22   4.7 Main changes in Ericsson GSM system R10/BSS R10 24   5 Engineering guidelines 24   6 Parameters 26   6.1 Main controlling parameters 26   6.2 Parameters for special adjustments 26   6.3 Value ranges and default values 28   7 References 29

    標簽: EDGE 信道分配

    上傳時間: 2013-11-12

    上傳用戶:ainimao

  • lpc2292/lpc2294 pdf datasheet

    The LPC2292/2294 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 256 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 pct with minimal performance penalty. With their 144-pin package, low power consumption, various 32-bit timers, 8-chAnnel 10-bit ADC, 2/4 (LPC2294) advanced CAN chAnnels, PWM chAnnels and up to nine external interrupt pins these microcontrollers are particularly suitable for automotive and industrial control applications as well as medical systems and fault-tolerant maintenance buses. The number of available fast GPIOs ranges from 76 (with external memory) through 112 (single-chip). With a wide range of additional serial communications interfaces, they are also suited for communication gateways and protocol converters as well as many other general-purpose applications. Remark: Throughout the data sheet, the term LPC2292/2294 will apply to devices with and without the /00 or /01 suffix. The suffixes /00 and /01 will be used to differentiate from other devices only when necessary.

    標簽: lpc datasheet 2292 2294

    上傳時間: 2014-12-30

    上傳用戶:aysyzxzm

  • 克服了正交頻分復用(OFDM)和IEEE 1901.2智能電網(wǎng)通信的挑戰(zhàn)

    Abstract: While many questions still surround the creation and deployment of the smart grid, the need for a reliablecommunications infrastructure is indisputable. Developers of the IEEE 1901.2 standard identified difficult chAnnel conditionscharacteristic of low-frequency powerline communications and implemented an orthogonal frequency division multiplexing (OFDM)architecture using advanced modulation and chAnnel-coding techniques. This strategy helped to ensure a robust communicationsnetwork for the smart grid.

    標簽: 1901.2 OFDM IEEE 正交頻分復用

    上傳時間: 2013-10-18

    上傳用戶:myworkpost

  • LPC314x系列ARM微控制器用戶手冊

    The NXP LPC314x combine a 270 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, three chAnnel10-bit A/D, and a myriad of serial and parallel interfaces in a single chip targeted atconsumer, industrial, medical, and communication markets. To optimize system powerconsumption, the LPC314x have multiple power domains and a very flexible ClockGeneration Unit (CGU) that provides dynamic clock gating and scaling.

    標簽: 314x LPC 314 ARM

    上傳時間: 2013-10-11

    上傳用戶:yuchunhai1990

  • MAX338/MAX339的英文數(shù)據(jù)手冊

      本軟件是關于MAX338, MAX339的英文數(shù)據(jù)手冊:MAX338, MAX339   8通道/雙4通道、低泄漏、CMOS模擬多路復用器   The MAX338/MAX339 are monolithic, CMOS analog multiplexers (muxes). The 8-chAnnel MAX338 is designed to connect one of eight inputs to a common output by control of a 3-bit binary address. The dual, 4-chAnnel MAX339 is designed to connect one of four inputs to a common output by control of a 2-bit binary address. Both devices can be used as either a mux or a demux. On-resistance is 400Ω max, and the devices conduct current equally well in both directions.   These muxes feature extremely low off leakages (less than 20pA at +25°C), and extremely low on-chAnnel leakages (less than 50pA at +25°C). The new design offers guaranteed low charge injection (1.5pC typ) and electrostatic discharge (ESD) protection greater than 2000V, per method 3015.7. These improved muxes are pin-compatible upgrades for the industry-standard DG508A and DG509A. For similar Maxim devices with lower leakage and charge injection but higher on-resistance, see the MAX328 and MAX329.

    標簽: MAX 338 339 英文

    上傳時間: 2013-11-12

    上傳用戶:18711024007

  • Virtex-5 GTP Transceiver Wizar

    The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibrechAnnel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts

    標簽: Transceiver Virtex Wizar GTP

    上傳時間: 2013-10-20

    上傳用戶:dave520l

  • XAPP713 -Virtex-4 RocketIO誤碼率測試器

      The data plane of the reference design consists of a configurable multi-chAnnel XBERT modulethat generates and checks high-speed serial data transmitted and received by the MGTs. EachchAnnel in the XBERT module consists of two MGTs (MGTA and MGTB), which physicallyoccupy one MGT tile in the Virtex-4 FPGA. Each MGT has its own pattern checker, but bothMGTs in a chAnnel share the same pattern generator. Each chAnnel can load a differentpattern. The MGT serial rate depends on the reference clock frequency and the internal PMAdivider settings. The reference design can be scaled anywhere from one chAnnel (two MGTs)to twelve chAnnels (twenty-four MGTs).

    標簽: RocketIO Virtex XAPP 713

    上傳時間: 2013-12-25

    上傳用戶:jkhjkh1982

  • HDMI一致性測試

      The high defi nition multimedia interface (HDMI) is fastbecoming the de facto standard for passing digitalaudio and video data in home entertainment systems.This standard includes an I2C type bus called a displaydata chAnnel (DDC) that is used to pass extended digitalinterface data (EDID) from the sinkdevice (such as adigital TV) to the source device (such as a digital A/Vreceiver). EDID includes vital information on the digitaldata formats that the sink device can accept. The HDMIspecifi cation requires that devices have less than 50pFof input capacitance on their DDC bus lines, which canbe very diffi cult to meet. The LTC®4300A’s capacitancebuffering feature allows devices to pass the HDMI DDCinput capacitance compliance test with ease.

    標簽: HDMI 測試

    上傳時間: 2013-11-21

    上傳用戶:tian126vip

  • LT5528 WCDMA ACPR和AltCPR測量

      ACPR (adjacent chAnnel power ratio), AltCPR (alternatechAnnel power ratio), and noise are important performancemetrics for digital communication systems thatuse, for example, WCDMA (wideband code division multipleaccess) modulation. ACPR and AltCPR are bothmeasures of spectral regrowth. The power in the WCDMAcarrier is measured using a 5MHz measurement bandwidth;see Figure 1. In the case of ACPR, the total powerin a 3.84MHz bandwidth centered at 5MHz (the carrierspacing) away from the center of the outermost carrier ismeasured and compared to the carrier power. The resultis expressed in dBc. For AltCPR, the procedure is thesame, except we center the measurement 10MHz awayfrom the center of the outermost carrier.

    標簽: AltCPR WCDMA 5528 ACPR

    上傳時間: 2013-11-02

    上傳用戶:maricle

主站蜘蛛池模板: 阿拉尔市| 渭南市| 崇仁县| 林州市| 图木舒克市| 措美县| 丘北县| 淮安市| 江孜县| 姜堰市| 休宁县| 察雅县| 阿勒泰市| 托克托县| 喜德县| 阳城县| 凭祥市| 利津县| 鹿泉市| 冷水江市| 柘城县| 太谷县| 永平县| 和平区| 吉安县| 渭源县| 杨浦区| 南城县| 临颍县| 宁远县| 塔城市| 西和县| 琼海市| 广元市| 平顶山市| 龙泉市| 孟津县| 翁源县| 上蔡县| 盈江县| 尖扎县|