The XA-S3 is a member of Philips Semiconductors’ XA (eXtended Architecture) family of high performance 16-bit single-chip Microcontrollers. The XA-S3 combines many powerful peripherals on one chip. Therefore, it is suited for general multipurpose high performance embedded control functions.One of the on-chip peripherals is the I2C bus interface. This report describes worked-out driver software (written in C) to program / use the I2C interface of the XA-S3. The driver software, together with a demo program and interface software routines offer the user a quick start in writing a comPLete I2C - XAS3 system application.
上傳時(shí)間： 2013-11-10
上傳用戶：liaofamous
有兩種方式可以讓設(shè)備和應(yīng)用程序之間聯(lián)系：1. 通過為設(shè)備創(chuàng)建的一個(gè)符號(hào)鏈；2. 通過輸出到一個(gè)接口WDM驅(qū)動(dòng)程序建議使用輸出到一個(gè)接口而不推薦使用創(chuàng)建符號(hào)鏈的方法。這個(gè)接口保證PDO的安全，也保證安全地創(chuàng)建一個(gè)惟一的、獨(dú)立于語(yǔ)言的訪問設(shè)備的方法。一個(gè)應(yīng)用程序使用Win32APIs來調(diào)用設(shè)備。在某個(gè)Win32 APIs和設(shè)備對(duì)象的分發(fā)函數(shù)之間存在一個(gè)映射關(guān)系。獲得對(duì)設(shè)備對(duì)象訪問的第一步就是打開一個(gè)設(shè)備對(duì)象的句柄。 用符號(hào)鏈打開一個(gè)設(shè)備的句柄為了打開一個(gè)設(shè)備，應(yīng)用程序需要使用CreateFile。如果該設(shè)備有一個(gè)符號(hào)鏈出口，應(yīng)用程序可以用下面這個(gè)例子的形式打開句柄：hDevice = CreateFile("\\\\.\\OMNIPORT3", GENERIC_READ | GENERIC_WRITE,FILE_SHARE_READ, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL ,NULL);文件路徑名的前綴“\\.\”告訴系統(tǒng)本調(diào)用希望打開一個(gè)設(shè)備。這個(gè)設(shè)備必須有一個(gè)符號(hào)鏈，以便應(yīng)用程序能夠打開它。有關(guān)細(xì)節(jié)查看有關(guān)Kdevice和CreateLink的內(nèi)容。在上述調(diào)用中第一個(gè)參數(shù)中前綴后的部分就是這個(gè)符號(hào)鏈的名字。注意：CreatFile中的第一個(gè)參數(shù)不是Windows 98/2000中驅(qū)動(dòng)程序(.sys文件)的路徑。是到設(shè)備對(duì)象的符號(hào)鏈。如果使用DriverWizard產(chǎn)生驅(qū)動(dòng)程序，它通常使用類KunitizedName來構(gòu)成設(shè)備的符號(hào)鏈。這意味著符號(hào)鏈名有一個(gè)附加的數(shù)字，通常是0。例如：如果鏈接名稱的主干是L“TestDevice”那么在CreateFile中的串就該是“\\\\.\\TestDevice0”。如果應(yīng)用程序需要被覆蓋的I/O，第六個(gè)參數(shù)(Flags)必須或上FILE_FLAG_OVERLAPPED。 使用一個(gè)輸出接口打開句柄用這種方式打開一個(gè)句柄會(huì)稍微麻煩一些。DriverWorks庫(kù)提供兩個(gè)助手類來使獲得對(duì)該接口的訪問容易一些，這兩個(gè)類是CDeviceInterface, 和 CdeviceInterfaceClass。CdeviceInterfaceClass類封裝了一個(gè)設(shè)備信息集，該信息集包含了特殊類中的所有設(shè)備接口信息。應(yīng)用程序能有用CdeviceInterfaceClass類的一個(gè)實(shí)例來獲得一個(gè)或更多的CdeviceInterface類的實(shí)例。CdeviceInterface類是一個(gè)單一設(shè)備接口的抽象。它的成員函數(shù)DevicePath()返回一個(gè)路徑名的指針，該指針可以在CreateFile中使用來打開設(shè)備。下面用一個(gè)小例子來顯示這些類最基本的使用方法：extern GUID TestGuid;HANDLE OpenByInterface( GUID* pClassGuid, DWORD instance, PDWORD pError){ CDeviceInterfaceClass DevClass(pClassGuid, pError); if (*pError != ERROR_SUCCESS) return INVALID_HANDLE_VALUE; CDeviceInterface DevInterface(&DevClass, instance, pError); if (*pError != ERROR_SUCCESS) return INVALID_HANDLE_VALUE; cout << "The device path is " << DevInterface.DevicePath() << endl; HANDLE hDev; hDev = CreateFile( DevInterface.DevicePath(), GENERIC_READ | GENERIC_WRITE, FILE_SHARE_READ | FILE_SHARE_WRITE, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, NULL ); if (hDev == INVALID_HANDLE_VALUE) *pError = GetLastError(); return hDev;} 在設(shè)備中執(zhí)行I/O操作一旦應(yīng)用程序獲得一個(gè)有效的設(shè)備句柄，它就能使用Win32 APIs來產(chǎn)生到設(shè)備對(duì)象的IRPs。下面的表顯示了這種對(duì)應(yīng)關(guān)系。Win32 API DRIVER_FUNCTION_xxxIRP_MJ_xxx KDevice subclass member function CreateFile CREATE Create ReadFile READ Read WriteFile WRITE Write DeviceIoControl DEVICE_CONTROL DeviceControl CloseHandle CLOSECLEANUP CloseCleanUp 需要解釋一下設(shè)備類成員的Close和CleanUp：CreateFile使內(nèi)核為設(shè)備創(chuàng)建一個(gè)新的文件對(duì)象。這使得多個(gè)句柄可以映射同一個(gè)文件對(duì)象。當(dāng)這個(gè)文件對(duì)象的最后一個(gè)用戶級(jí)句柄被撤銷后，I/O管理器調(diào)用CleanUp。當(dāng)沒有任何用戶級(jí)和核心級(jí)的對(duì)文件對(duì)象的訪問的時(shí)候，I/O管理器調(diào)用Close。如果被打開的設(shè)備不支持指定的功能，則調(diào)用相應(yīng)的Win32將引起錯(cuò)誤（無效功能）。以前為Windows95編寫的VxD的應(yīng)用程序代碼中可能會(huì)在打開設(shè)備的時(shí)候使用FILE_FLAG_DELETE_ON_CLOSE屬性。在Windows NT/2000中，建議不要使用這個(gè)屬性，因?yàn)樗鼘?dǎo)致沒有特權(quán)的用戶企圖打開這個(gè)設(shè)備，這是不可能成功的。I/O管理器將ReadFile和WriteFile的buff參數(shù)轉(zhuǎn)換成IRP域的方法依賴于設(shè)備對(duì)象的屬性。當(dāng)設(shè)備設(shè)置DO_DIRECT_IO標(biāo)志，I/O管理器將buff鎖住在存儲(chǔ)器中，并且創(chuàng)建了一個(gè)存儲(chǔ)在IRP中的MDL域。一個(gè)設(shè)備可以通過調(diào)用Kirp::Mdl來存取MDL。當(dāng)設(shè)備設(shè)置DO_BUFFERED_IO標(biāo)志，設(shè)備對(duì)象分別通過KIrp::BufferedReadDest或 KIrp::BufferedWriteSource為讀或?qū)懖僮鳙@得buff地址。當(dāng)設(shè)備不設(shè)置DO_BUFFERED_IO標(biāo)志也不設(shè)置DO_DIRECT_IO，內(nèi)核設(shè)置IRP 的UserBuffer域來對(duì)應(yīng)ReadFile或WriteFile中的buff參數(shù)。然而，存儲(chǔ)區(qū)并沒有被鎖住而且地址只對(duì)調(diào)用進(jìn)程有效。驅(qū)動(dòng)程序可以使用KIrp::UserBuffer來存取IRP域。對(duì)于DeviceIoControl調(diào)用，buffer參數(shù)的轉(zhuǎn)換依賴于特殊的I/O控制代碼，它不在設(shè)備對(duì)象的特性中。宏CTL_CODE（在winioctl.h中定義）用來構(gòu)造控制代碼。這個(gè)宏的其中一個(gè)參數(shù)指明緩沖方法是METHOD_BUFFERED, METHOD_IN_DIRECT, METHOD_OUT_DIRECT, 或METHOD_NEITHER。下面的表顯示了這些方法和與之對(duì)應(yīng)的能獲得輸入緩沖與輸出緩沖的KIrp中的成員函數(shù)：Method Input Buffer Parameter Output Buffer Parameter METHOD_BUFFERED KIrp::IoctlBuffer KIrp::IoctlBuffer METHOD_IN_DIRECT KIrp::IoctlBuffer KIrp::Mdl METHOD_OUT_DIRECT KIrp::IoctlBuffer KIrp::Mdl METHOD_NEITHER KIrp::IoctlType3InputBuffer KIrp::UserBuffer 如果控制代碼指明METHOD_BUFFERED，系統(tǒng)分配一個(gè)單一的緩沖來作為輸入與輸出。驅(qū)動(dòng)程序必須在向輸出緩沖放數(shù)據(jù)之前拷貝輸入數(shù)據(jù)。驅(qū)動(dòng)程序通過調(diào)用KIrp::IoctlBuffer獲得緩沖地址。在完成時(shí)，I/O管理器從系統(tǒng)緩沖拷貝數(shù)據(jù)到提供給Ring 3級(jí)調(diào)用者使用的緩沖中。驅(qū)動(dòng)程序必須在結(jié)束前存儲(chǔ)拷貝到IRP的Information成員中的數(shù)據(jù)個(gè)數(shù)。如果控制代碼不指明METHOD_IN_DIRECT或METHOD_OUT_DIRECT，則DeviceIoControl的參數(shù)呈現(xiàn)不同的含義。參數(shù)InputBuffer被拷貝到一個(gè)系統(tǒng)緩沖，這個(gè)緩沖驅(qū)動(dòng)程序可以通過調(diào)用KIrp::IoctlBuffer。參數(shù)OutputBuffer被映射到KMemory對(duì)象，驅(qū)動(dòng)程序?qū)@個(gè)對(duì)象的訪問通過調(diào)用KIrp::Mdl來實(shí)現(xiàn)。對(duì)于METHOD_OUT_DIRECT，調(diào)用者必須有對(duì)緩沖的寫訪問權(quán)限。注意，對(duì)METHOD_NEITHER，內(nèi)核只提供虛擬地址；它不會(huì)做映射來配置緩沖。虛擬地址只對(duì)調(diào)用進(jìn)程有效。這里是一個(gè)用METHOD_BUFFERED的例子：首先，使用宏CTL_CODE來定義一個(gè)IOCTL代碼：#define IOCTL_MYDEV_GET_FIRMWARE_REV \CTL_CODE (FILE_DEVICE_UNKNOWN,0,METHOD_BUFFERED,FILE_ANY_ACCESS)現(xiàn)在使用一個(gè)DeviceIoControl調(diào)用：BOOLEAN b;CHAR FirmwareRev[60];ULONG FirmwareRevSize;b = DeviceIoControl(hDevice, IOCTL_MYDEV_GET_VERSION_STRING, NULL, // no input 注意，這里放的是包含有執(zhí)行操作命令的字符串指針 0, FirmwareRev, //這里是output串指針，存放從驅(qū)動(dòng)程序中返回的字符串。sizeof(FirmwareRev),& FirmwareRevSize, NULL // not overlapped I/O );如果輸出緩沖足夠大，設(shè)備拷貝串到里面并將拷貝的資結(jié)束設(shè)置到FirmwareRevSize中。在驅(qū)動(dòng)程序中，代碼看起來如下所示：const char* FIRMWARE_REV = "FW 16.33 v5";NTSTATUS MyDevice::DeviceControl( KIrp I ){ ULONG fwLength=0; switch ( I.IoctlCode() ) { case IOCTL_MYDEV_GET_FIRMWARE_REV: fwLength = strlen(FIRMWARE_REV)+1; if (I.IoctlOutputBufferSize() >= fwLength) { strcpy((PCHAR)I.IoctlBuffer(),FIRMWARE_REV); I.Information() = fwLength; return I.comPLete(STATUS_SUCCESS); } else { } case . . . } }
標(biāo)簽： 驅(qū)動(dòng)程序 應(yīng)用程序 接口
上傳時(shí)間： 2013-10-17
上傳用戶：gai928943
設(shè)計(jì)一種應(yīng)用于某全地形ATV車載武器裝置中的中控系統(tǒng)，該系統(tǒng)設(shè)計(jì)是以TMS320F2812型DSP為核心，采用模塊化設(shè)計(jì)思想，對(duì)其硬件部分進(jìn)行系統(tǒng)設(shè)計(jì)，能夠完成對(duì)武器裝置高低、回轉(zhuǎn)方向的運(yùn)動(dòng)控制，實(shí)現(xiàn)靜止或行進(jìn)狀態(tài)中對(duì)目標(biāo)物的測(cè)距，自動(dòng)瞄準(zhǔn)以及按既定發(fā)射模式發(fā)射彈丸和各項(xiàng)安全性能檢測(cè)等功能。通過編制相應(yīng)的軟件，對(duì)其進(jìn)行系統(tǒng)調(diào)試，驗(yàn)證了該設(shè)計(jì)運(yùn)行穩(wěn)定。 Abstract: A central control system applied to an ATV vehicle weapons is designed. The system design is based on TMS320F2812 DSP as the core， uses modular design for its hardware parts. The central control system can comPLete the motion control of the level of weapons and equipment， rotation direction， to achieve a state of static or moving objects on the target ranging， auto-targeting and according to the established target and the projectile and the launch of the security performance testing and other functions. Through the development of appropriate software and to carry out system testing to verify the stability of this design and operation.
標(biāo)簽： ATV-ATT DSP 中控系統(tǒng)
上傳時(shí)間： 2013-11-02
上傳用戶：jshailingzzh
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their productsor to discontinue any product or service without notice, and advise customers to obtain the latestversion of relevant information to verify, before placing orders, that information being relied onis current and comPLete. All products are sold subject to the terms and conditions of sale suppliedat the time of order acknowledgement, including those pertaining to warranty, patentinfringement, and limitation of liability
上傳時(shí)間： 2013-12-26
上傳用戶：凌云御清風(fēng)
針對(duì)嵌入式機(jī)器視覺系統(tǒng)向獨(dú)立化、智能化發(fā)展的要求，介紹了一種嵌入式視覺系統(tǒng)--智能相機(jī)。基于對(duì)智能相機(jī)體系結(jié)構(gòu)、組成模塊和圖像采集、傳輸和處理技術(shù)的分析，對(duì)國(guó)內(nèi)外的幾款智能相機(jī)進(jìn)行比較。綜合技術(shù)發(fā)展現(xiàn)狀，提出基于FPGA+DSP模式的硬件平臺(tái)，并提出智能相機(jī)的發(fā)展方向。分析結(jié)果表明，該系統(tǒng)設(shè)計(jì)可以實(shí)現(xiàn)脫離PC運(yùn)行，完成圖像獲取與分析，并作出相應(yīng)輸出。 Abstract: This paper introduced an embedded vision system-intelligent camera ，which was for embedded machine vision systems to an independent and intelligent development requirements. Intelligent camera architecture， component modules and image acquisition， transmission and processing technology were analyzed. After comparing integrated technology development of several intelligent cameras at home and abroad， the paper proposed the hardware platform based on FPGA+DSP models and made clear direction of development of intelligent cameras. On the analysis of the design， the results indicate that the system can run from the PC independently to comPLete the image acquisition and analysis and give a corresponding output.
標(biāo)簽： FPGA DSP 模式 智能相機(jī)
上傳時(shí)間： 2013-10-24
上傳用戶：bvdragon
針對(duì)傳統(tǒng)集成電路（ASIC）功能固定、升級(jí)困難等缺點(diǎn)，利用FPGA實(shí)現(xiàn)了擴(kuò)頻通信芯片STEL-2000A的核心功能。使用ISE提供的DDS IP核實(shí)現(xiàn)NCO模塊，在下變頻模塊調(diào)用了硬核乘法器并引入CIC濾波器進(jìn)行低通濾波，給出了DQPSK解調(diào)的原理和實(shí)現(xiàn)方法，推導(dǎo)出一種簡(jiǎn)便的引入?仔/4固定相移的實(shí)現(xiàn)方法。采用模塊化的設(shè)計(jì)方法使用VHDL語(yǔ)言編寫出源程序，在Virtex-II Pro 開發(fā)板上成功實(shí)現(xiàn)了整個(gè)系統(tǒng)。測(cè)試結(jié)果表明該系統(tǒng)正確實(shí)現(xiàn)了STEL-2000A的核心功能。 Abstract: To overcome drawbacks of ASIC such as fixed functionality and upgrade difficulty, FPGA was used to realize the core functions of STEL-2000A. This paper used the DDS IP core provided by ISE to realize the NCO module, called hard core multiplier and implemented CIC filter in the down converter, described the principle and implementation detail of the demodulation of DQPSK, and derived a simple method to introduce a fixed phase shift of ?仔/4. The VHDL source code was designed by modularity method , and the comPLete system was successfully implemented on Virtex-II Pro development board. Test results indicate that this system successfully realize the core function of the STEL-2000A.
標(biāo)簽： STEL 2000 FPGA 擴(kuò)頻通信
上傳時(shí)間： 2013-11-06
上傳用戶：liu123
This application note describes a reference system which illustrates how to build an embeddedPowerPC® system using the Xilinx 1-Gigabit Ethernet Media Access Controller processor core.This system has the PLB_Gemac configured to use Scatter/Gather Direct Memory Access andthe Serializer/Deserializer (SerDes) interface. This application note describes how to set up thespecific clocking structure required for the SerDes interface and the constraints to be added tothe UCF file. This reference system is comPLete with a standalone software application to testsome of the main features of this core, including access to registers, DMA capabilities, transmitand receive in loopback mode. This reference system is targeted for the ML300 evaluationboard.
上傳時(shí)間： 2013-11-01
上傳用戶：truth12
為提升虛擬儀器傳輸速率與實(shí)時(shí)性能，擴(kuò)展監(jiān)測(cè)范圍，在VC的軟件平臺(tái)上設(shè)計(jì)了一種全功能虛擬示波器。與傳統(tǒng)虛擬示波器相比，該系統(tǒng)采用嵌入式系統(tǒng)完成信號(hào)采集，采用工業(yè)以太網(wǎng)為傳輸介質(zhì)，通過線性插值算法和多線程編程思想，實(shí)現(xiàn)波形顯示、參數(shù)計(jì)算、頻譜分析以及波形存儲(chǔ)及回放功能。實(shí)驗(yàn)結(jié)果表明，該虛擬示波器可以實(shí)現(xiàn)20 kHz采樣頻率下的波形精確顯示，達(dá)到預(yù)期的各項(xiàng)指標(biāo)。 Abstract: o enhance the transfer rate and real-time of virtual instrument performance， expand scope of monitoring， this paper uses the VCs software platform to design a fully functional virtual oscilloscope. Compared with traditional virtual oscilloscope， this system adopts the embedded system to comPLete the data acquisition， industrial Ethernet as the transmission medium used by the linear interpolation algorithm and multi-threaded programming ideas， namely to achieve waveform display， parameter calculation， spectrum analysis and waveform storage and playback. Experimental results show that the virtual oscilloscope can accurately display the waveform with 20kHz sampling frequency， and achieve the desired targets.
標(biāo)簽： 以太網(wǎng) 虛擬 波器設(shè)計(jì)
上傳時(shí)間： 2013-11-25
上傳用戶：wbwyl
Agilent AN 154 S-Parameter Design Application Note S參數(shù)的設(shè)計(jì)與應(yīng)用 The need for new high-frequency, solid-state circuitdesign techniques has been recognized both by microwaveengineers and circuit designers. These engineersare being asked to design solid state circuitsthat will operate at higher and higher frequencies.The development of microwave transistors andAgilent Technologies’ network analysis instrumentationsystems that permit comPLete network characterizationin the microwave frequency rangehave greatly assisted these engineers in their work.The Agilent Microwave Division’s lab staff hasdeveloped a high frequency circuit design seminarto assist their counterparts in R&D labs throughoutthe world. This seminar has been presentedin a number of locations in the United States andEurope.From the experience gained in presenting this originalseminar, we have developed a four-part videotape, S-Parameter Design Seminar. While the technologyof high frequency circuit design is everchanging, the concepts upon which this technologyhas been built are relatively invariant.The content of the S-Parameter Design Seminar isas follows:
標(biāo)簽： S參數(shù)
上傳時(shí)間： 2013-12-19
上傳用戶：aa54
怎樣使用Nios II處理器來構(gòu)建多處理器系統(tǒng) Chapter 1. Creating Multiprocessor Nios II Systems Introduction to Nios II Multiprocessor Systems . . . . . . . . . . . . . . 1–1 Benefits of Hierarchical Multiprocessor Systems . . . . . . . . . . . . . . . 1–2 Nios II Multiprocessor Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Multiprocessor Tutorial Prerequisites . . . . . . . . . . . . . . . . . . . . . . . 1–3 Hardware Designs for Peripheral Sharing . . . . . . . . . . . .. . . . . . . . 1–3 Autonomous Multiprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3 Multiprocessors that Share Peripherals . . . . . . . . . . . . . . . . . . . . . . 1–4 Sharing Peripherals in a Multiprocessor System . . . . . . . . . . . . . . . . . 1–4 Sharing Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6 The Hardware Mutex Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7 Sharing Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 1–8 Overlapping Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8 Software Design Considerations for Multiple Processors . . .. . . . . 1–9 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9 Boot Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1–13 Debugging Nios II Multiprocessor Designs . . . . . . . . . . . . . . . . 1–15 Design Example: The Dining Philosophers’ Problem . . . . .. . . 1–15 Hardware and Software Requirements . . . . . . . . . . . . . . . .. . . 1–16 Installation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17 Creating the Hardware System . . . . . . . . . . . . . . .. . . . . . 1–17 Getting Started with the multiprocessor_tutorial_start Design Example 1–17 Viewing a Philosopher System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18 Philosopher System Pipeline Bridges . . . . . . . . . . . . . . . . . . . . . 1–19 Adding Philosopher Subsystems . . . . . . . . . . . . . . . . . . . . . . . . . . 1–21 Connecting the Philosopher Subsystems . . . . . . . . . . . . .. . . . . 1–22 Viewing the comPLete System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–27 Generating and Compiling the System . . . . . . . . . . . . . . . . . .. 1–28
上傳時(shí)間： 2013-11-21
上傳用戶：lo25643
蟲蟲下載站版權(quán)所有 京ICP備2021023401號(hào)-1
