PCI ExpressTM Architecture
Add-in Card Compliance Checklist for the PCI Express Base 1.0a SpecificationThe PCI Special Interest Group disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does the PCI Special Interest Group make a commitment to update the information contained herein.contact the PCI Special Interest Group office to obtain the latest revision of this checklistQuestions regarding the ths document or membership in the PCI Special Interest Group may be forwarded tPCI Special Interest Group5440 SW Westgate Drive #217Portland, OR 97221Phone: 503-291-2569Fax: 503-297-1090 DISCLAIMERThis document is provided "as is" with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample. The PCI SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein.
標(biāo)簽：
Architecture
ExpressTM
PCI
上傳時(shí)間：
2013-11-03
上傳用戶：gy592333
The MAX3243E device consists of three line drivers, five line receivers, and a dual charge-pump circuit with±15-kV ESD (HBM and IEC61000-4-2, Air-Gap Discharge) and ±8-kV ESD (IEC61000-4-2, contact Discharge)protection on serial-port connection pins. The device meets the requirements of TIA/EIA-232-F and provides theelectrical interface between an asynchronous communication controller and the serial-port connector. Thiscombination of drivers and receivers matches that needed for the typical serial port used in an IBM PC/AT, orcompatible. The charge pump and four small external capacitors allow operation from a single 3-V to 5.5-Vsupply. In addition, the device includes an always-active noninverting output (ROUT2B), which allowsapplications using the ring indicator to transmit data while the device is powered down. The device operates atdata signaling rates up to 250 kbit/s and a maximum of 30-V/ms driver output slew rate.
標(biāo)簽：
MULTICHANNEL
5.5
TO
RS
上傳時(shí)間：
2013-10-19
上傳用戶：ddddddd
