This example describes how to use the ADC and DMA to transfer continuously converted data from ADC to a data buffer. The ADC is configured to converts continuously ADC channel14. Each time an end of conversion occurs the DMA transfers, in circular mode, the converted data from ADC1 DR register to the ADC_ConvertedValue variable. The ADC1 clock is set to 14 MHz.
標簽： continuously ADC describes converted
上傳時間： 2014-01-03
上傳用戶：徐孺
This example provides a description of how to use a DMA channel to transfer a word data buffer from memory (Flash) to memory (RAM). The dedicated DMA channel is configured to transfer once a time a 32 word data buffer stored as constant in the Flash memory to another buffer in the RAM memory. The received data are stored in the DST_Buffer. The DMA channel transfer complete interrupt is enabled to generate an interrupt at the end of the buffer transfer. As soon as the transfer is completed an interrupt is generated and in the DMA channel interrupt routine the transfer complete interrupt pending bit is cleared. The data counter is stored before and after the transfer to show that all data has been transfered. TransferStatus gives the data transfer status where it is PASSED if transmitted and received data are the same otherwise it is FAILED
標簽： description provides transfer example
上傳時間： 2016-04-24
上傳用戶：ecooo
First of all we would like to thank God Almighty for giving us the strength and confidence in pursing the ambitions. We would like to thank our Examiner Professor Axel Jantsch for allowing us to do this under his guidance and encouragement. At the same time we would like to mention our sincere thanks to Mr. Said Zainali, Manager of FRAME ACCESS AB for giving all the required equipment and the technical support which helped us to finish this thesis. We would like to mention our gratitude to our fellow VACS team members who helped us a lot during difficult times.
標簽： confidence Almighty strength giving
上傳時間： 2013-12-01
上傳用戶：小碼農lz
Qpsk signal Processing Code The DSP code should be efficient and accurate to properly demodulate the incoming signal. The DSP can be coded strictly in “C” or C-language can be intermingled with assembly code.include Real Time Digital Signal Processor Code – Main.c file BER Test Code
標簽： Processing demodulate efficient accurate
上傳時間： 2014-08-10
上傳用戶：dancnc
A .zip file contains a series of scripts that were used in the MathWorks webinar "Using MATLAB to Develop Portfolio Optimization Models." The scripts generate 3D efficient frontiers for a universe of 44 stocks with time as the third axis. Additional scripts perform various ex-ante and ex-post analyses. Results are generated with and without market adjustments in the data. A readme.txt. file in the .zip folder describes each script and how to use it
標簽： MathWorks contains scripts webinar
上傳時間： 2014-01-04
上傳用戶：trepb001
oJPEG2000中DWT的MATLAB實現n the use of discrete cosine transform DCT jpeg compression Matlab source, simple and practical, the Notes have a good time
標簽： compression transform discrete MATLAB
上傳時間： 2013-12-14
上傳用戶：luopoguixiong
a screen handling program to provide a flashing message. You will have to design a screen layout for where messages are placed on the screen. You will also have to consider when to delay the program in order to give the user time to read the messages. That is, the program will use the curses library, signals and the sleep function.
標簽： screen handling flashing program
上傳時間： 2016-05-04
上傳用戶：chongcongying
FreeTTS is a speech synthesis system written entirely in the Java programming language. It is based upon Flite, a small, fast, run-time speech synthesis engine, which in turn is based upon University of Edinburgh s Festival Speech Synthesis System and Carnegie Mellon University s FestVox project.
標簽： programming synthesis entirely language
上傳時間： 2014-08-29
上傳用戶：cylnpy
K3:--- P1.6 K4:--- P1.7 BEEP:--- P3.7 K3 --- 控制按鍵 K4 --- 清零按鍵 開機顯示： SECOND-CLOCK 0 TIME 00:00:00:00 K3 --- 控制按鍵： 第一次按下時,開始計時。 顯示 BEGIN COUNT 1 TIME 00:00:01:88 第二次按下時,暫停計時。 顯示 PAUST COUNT 2 TIME 00:00:01:88 第三次按下時,累計計時。
標簽： SECOND-CLOCK K3 BEEP K4
上傳時間： 2016-05-10
上傳用戶：清風冷雨
I2C Slave module The module contains N accessable Registers when in read Process, all Registers are read at a time when in write Process, only the addressed register are Writeable.
標簽： Registers module accessable contains
上傳時間： 2016-05-13
上傳用戶：xauthu
