本文采用Altera公司的FPGA器件cyclone III系列EP3C10作為核心器件構(gòu)成了R-S（255，223）編碼系統(tǒng)；利用Quartus II 9.0作為硬件仿真平臺(tái)，用硬件描述語(yǔ)言Verilog_HDL實(shí)現(xiàn)編程，并且通過JTAG接口與EP3C10連接。R-S（Reed-Solomon）碼是一類糾錯(cuò)能力很強(qiáng)的特殊的非二進(jìn)制BCH碼，能應(yīng)對(duì)隨機(jī)性和突發(fā)性錯(cuò)誤，廣泛應(yīng)用于各種通信系統(tǒng)中和保密系統(tǒng)中。R-S（255，223）碼能夠檢測(cè)32字節(jié)長(zhǎng)度和糾錯(cuò)16字節(jié)長(zhǎng)度的連續(xù)數(shù)據(jù)錯(cuò)誤信息。
This SPI-mode SD Card controller is a free SOPC Builder component that can be used in any SOPC Builder system. The included example design runs on the Nios II Embedded Evaluation Kit, cyclone III edition (NEEK).
This SPI-mode SD Card controller is a free SOPC Builder component that can be used in any SOPC Builder system. The included example design runs on the Nios II Embedded Evaluation Kit, cyclone III edition (NEEK).
The Cyclone® III PCI development board provides a hardware platform for developing and
prototyping low-power, high-performance, logic-intensive PCI-based designs. The board provides a
high-density of the memory to facilitate the design and development of FPGA designs which need
huge memory storage, and also includes Low-Voltage Differential Signaling (LVDS) interface of
the High-Speed Terasic Connectors (HSTCs) for extra high-speed interface application.
