Hard-decision decodINg scheme
Codeword length (n) : 31 symbols.
Message length (k) : 19 symbols.
Error correction capability (t) : 6 symbols
One symbol represents 5 bit.
Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1
Generator polynomial, g(x) = a^15 a^21*X + a^6*X^2 + a^15*X^3 + a^25*X^4 + a^17*X^5 + a^18*X^6 + a^30*X^7 + a^20*X^8 + a^23*X^9 + a^27*X^10 + a^24*X^11 + X^12. Note: a = alpha, primitive element in GF(2^5) and a^i is root of g(x) for i = 19, 20, ..., 30.
Uses Verilog description with synthesizable RTL modelling.
Consists of 5 main blocks: SC (Syndrome Computation), KES (Key Equation Solver), CSEE (Chien Search and Error Evaluator), Controller and FIFO Register.
標(biāo)簽:
symbols
length
Hard-decision
Codeword
上傳時(shí)間:
2014-07-08
上傳用戶:曹云鵬
AES Core Modules In this document I describe components designated to encoding and decodINg
using AES.
aes enc — parametrizable component which can encrypt input data, using
128, 192 and 256 bit key,
• aes dec — parametrizable component which can decrypt input data, using
128, 192 and 256 bit key,
• key expansion — parametrizable component which can produce key expansion,
using 128, 192 and 256 bit key,
標(biāo)簽:
components
designated
document
describe
上傳時(shí)間:
2015-12-22
上傳用戶:Late_Li