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  • 《Verilog HDL 硬件描述語言》

    ·詳細(xì)說明:正式出版物《Verilog HDL 硬件描述語言》一書的精美 PDF 電子版。- Official publication Verilog HDL Hardware description Language a book fine PDF electron version.目      錄譯者序前言第1章   簡(jiǎn)介&n

    標(biāo)簽: nbsp Verilog HDL 硬件描述語言

    上傳時(shí)間: 2013-07-02

    上傳用戶:6404552

  • 硬件描述語言Verilog(第四版)

    ·【原書名】 The Verilog Hardware description Language(Fourth Edition) 【原出版社】 Kluwer Academic Publishers  【作者】 Donald E.Thomas &

    標(biāo)簽: Verilog 硬件描述語言

    上傳時(shí)間: 2013-04-24

    上傳用戶:q123321

  • SystemVerilog for Design

    ·SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware description Language (Verilog HDL). These extensions address two major aspects of HDL-based design. First, modeling ver

    標(biāo)簽: nbsp SystemVerilog Design for

    上傳時(shí)間: 2013-07-14

    上傳用戶:ainimao

  • US Navy VHDL Modelling Guide

      This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC Hardwaredescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.

    標(biāo)簽: Modelling Guide Navy VHDL

    上傳時(shí)間: 2014-12-23

    上傳用戶:xinhaoshan2016

  • VHDL,Verilog,System verilog比較

      本文簡(jiǎn)單討論并總結(jié)了VHDL、Verilog,System verilog 這三中語言的各自特點(diǎn)和區(qū)別As the number of enhancements to variousHardware description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.

    標(biāo)簽: Verilog verilog System VHDL

    上傳時(shí)間: 2013-10-16

    上傳用戶:牛布牛

  • ISM射頻產(chǎn)品的晶體頻率計(jì)算

    Abstract: Many industrial/scientific/medical (ISM) band radio frequency (RF) products use crystal oscillators to generate areference for the phase-locked loop (PLL)-based local oscillator (LO). This tutorial provides a basic description of theISM-RF Crystal Calculator, which can be used to calculate various impacts on crystal frequency accuracy and startupmargin for such an LO.  

    標(biāo)簽: ISM 射頻 晶體頻率 計(jì)算

    上傳時(shí)間: 2013-11-15

    上傳用戶:JasonC

  • 加載,感應(yīng)DAC應(yīng)用

    Abstract: This article discusses application circuits for Maxim force/sense digital-to-analog converters (DACs). Applications include:selectable fixed-gain DAC, programmable gain DAC, photodiode bias control, amperometric sensor control, digitally programmablecurrent source, Kelvin load sensing, temperature sensing, and high current DAC output. A brief description of the various DAC outputconfigurations is also given.

    標(biāo)簽: DAC

    上傳時(shí)間: 2013-11-04

    上傳用戶:youmo81

  • 你的PLD是亞穩(wěn)態(tài)嗎

      This application note provides a detailed description of themetastable behavior in PLDs from both circuit and statisticalviewpoints. Additionally, the information on the metastablecharacteristics of Cypress PLDs presented here can help youachieve any desired degree of reliability.

    標(biāo)簽: PLD 亞穩(wěn)態(tài)

    上傳時(shí)間: 2013-10-23

    上傳用戶:gtzj

  • 開放式匯編器系統(tǒng)的設(shè)計(jì)

    匯編器在微處理器的驗(yàn)證和應(yīng)用中舉足輕重,如何設(shè)計(jì)通用的匯編器一直是研究的熱點(diǎn)之一。本文提出了一種開放式的匯編器系統(tǒng)設(shè)計(jì)思想,在匯編語言與機(jī)器語言間插入中間代碼CMDL(code mapping description language)語言,打破匯編語言與機(jī)器語言的直接映射關(guān)系,由此建立起一套描述匯編語言與機(jī)器語言的開放式映射體系。基于此開放式映射體系開發(fā)了一套匯編器系統(tǒng),具有較高層次上的通用性和可移植性。【關(guān)鍵詞】指令集,CMDL,匯編器,開放式 Design of Retargetable Assembler System Liu Ling Feng Wen Nan Wang Ying Chun Jiang An Ping Ji Li Jiu IME of Peking University, 100871【摘要】An assembler plays a very important role in the field of microprocessor verifications and applications, thus how to build a retargetable assembler system has been a hotspot in this field for long time. This paper presents a new method about the retargetable assembler system design.It provides a kind of language CMDL, code mapping description language. During the process of assembling, assembler languages are firstly translated to CMDL, and then mapped to the machine codes. In an other word, CMDL is inserted between assembler languages and machine codes during the translation procedure. As a medium code, CMDL has a lot of features, such as high extraction, strong descript capabilities. It can describe almost all attributes of assembler languages. By breaking the direct mapping relationship between assembler languages and machine codes, the complexities of machine codes are hided to the users, therefore, the new retargetable assembler system has higher retargetable level by converting the mapping from assembler languages and machine codes to assembler languages and CMDL, and implementationof it becomes easier. Based on the new mapping system structure, a retargetable assemblersystem is developed. It proved the whole system has good retargetability and implantability.【關(guān)鍵詞】instruction set, symbol table, assembler, lexical analysis, retargetability

    標(biāo)簽: 開放式 匯編器

    上傳時(shí)間: 2013-10-10

    上傳用戶:meiguiweishi

  • MPC106 PCI橋/存儲(chǔ)器控制器硬件規(guī)范說明

    The Motorola MPC106 PCI bridge/memory controller provides a PowerPCªmicroprocessor common hardware reference platform (CHRPª) compliant bridgebetween the PowerPC microprocessor family and the Peripheral Component Interconnect(PCI) bus. In this document, the term Ô106Õ is used as an abbreviation for the phraseÔMPC106 PCI bridge/memory controllerÕ. This document contains pertinent physicalcharacteristics of the 106. For functional characteristics refer to theMPC106 PCI Bridge/Memory Controller UserÕs Manual.This document contains the following topics:Topic PageSection 1.1, ÒOverviewÓ 2Section 1.2, ÒFeaturesÓ 3Section 1.3, ÒGeneral ParametersÓ 5Section 1.4, ÒElectrical and Thermal CharacteristicsÓ 5Section 1.5, ÒPin AssignmentsÓ 17Section 1.6, ÒPinout Listings 18Section 1.7, ÒPackage descriptionÓ 22Section 1.8, ÒSystem Design InformationÓ 24Section 1.9, ÒDocument Revision HistoryÓ 29Section 1.10, ÒOrdering InformationÓ 29

    標(biāo)簽: MPC 106 PCI 存儲(chǔ)器

    上傳時(shí)間: 2013-11-04

    上傳用戶:as275944189

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