基于PIC單片機(jī)的低功耗讀卡器硬件設(shè)計(jì):本文提出了一個(gè)完整的基于串口的智能讀卡器子系統(tǒng)設(shè)計(jì)方案并將其實(shí)現(xiàn)。讀卡器的設(shè)計(jì)突出了小型化的要求，全部器件使用貼片封裝。為了減小讀卡器的體積，設(shè)計(jì)中還使用了串口竊電的技術(shù)，使用串口信號(hào)線直接給讀卡器供電。為此，讀卡器使用了省電的設(shè)計(jì)，采用了省電的集成電路，并大膽簡(jiǎn)化了許多傳統(tǒng)的設(shè)計(jì)電路。關(guān)鍵字： 讀卡器， 單片機(jī)， 串口竊電 Abstract： This paper aims to put forward a complete design of Smart IC card reader based onSerial Port and propose the way of realizing it for the purpose of Network Security. SMD isadopted to make Smart IC reader smaller in this design. To reduce the volume of Smart ICreader， Serial Port powered technology is employed to get power from the signal line of Serial Port. For this reason， low-power consumption components are adopted in the design and some traditional designs are simplified to reduce the power consumption.Keywords： Card Reader； Single-chip Computer； Serial Port Powered IC 卡系統(tǒng)保存了加密算法所需要的工作密鑰，供加密算法對(duì)網(wǎng)絡(luò)上傳輸?shù)臄?shù)據(jù)加密使用，是整個(gè)系統(tǒng)網(wǎng)絡(luò)安全的核心。在IC 卡子系統(tǒng)中，讀卡器是一個(gè)重要的部分。它起著管理IC卡、在IC 卡和PC或網(wǎng)絡(luò)計(jì)算機(jī)間傳遞數(shù)據(jù)的重要作用。本文以一片PIC單片機(jī)為核心完成了基于RS232 串口的讀卡器的硬件設(shè)計(jì)。
上傳時(shí)間： 2014-04-14
上傳用戶：wanghui2438
This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs. Introduction The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas around machines such as fast-moving robots, and distributed control systems in process automation equipment such as those used in petrochemical plants. The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was developed in the mid-1980s and has been revised several times to cover the technical advances in various industries. In addition, derivative standards have been developed for specific markets and applications that prescribe the particular requirements on functional safety systems in these industry applications. Example applications include process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC 62304), automotive (ISO 26262), power generation, distribution, and transportation. 圖Figure 1. Local Safety System
標(biāo)簽： FPGA 安全系統(tǒng)
上傳時(shí)間： 2013-11-05
上傳用戶：維子哥哥
Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective solution. Maxim's 3GPP TS25.104-compliant transceiver solution is presented along withcomplete radio reference designs such as RD2550. For more information on the RD2550, see reference design 5364, "FemtocellRadio Reference designs Using the MAX2550–MAX2553 Transceivers."
標(biāo)簽： Base-Station Applications Single-Chip Transceiver
上傳時(shí)間： 2013-11-07
上傳用戶：songrui
In the past decade, the size and complexity of manyFPGA designs exceeds the time and resourcesavailable to most design teams, making the use andreuse of Intellectual Property (IP) imperative.However, integrating numerous IP blocks acquiredfrom both internal and external sources can be adaunting challenge that often extends, rather thanshortens, design time. As today's designs integrateincreasing amounts of functionality, it is vital thatdesigners have access to proven, up-to-date IP fromreliable sources.
上傳時(shí)間： 2013-11-15
上傳用戶：lyy1234
Design techniques for electronic systems areconstantly changing. In industries at the heart of thedigital revolution, this change is especially acute.Functional integration, dramatic increases incomplexity, new standards and protocols, costconstraints, and increased time-to-market pressureshave bolstered both the design challenges and theopportunities to develop modern electronic systems.One trend driving these changes is the increasedintegration of core logic with previously discretefunctions to achieve higher performance and morecompact board designs.
標(biāo)簽： System Xilinx FPGA 151
上傳時(shí)間： 2014-12-28
上傳用戶：康郎
This application note contains a reference design consisting of HDL IP and Xilinx AdvancedConfiguration Environment (ACE) software utilities that give designers great flexibility increating in-system programming (ISP) solutions. In-system programming support allowsdesigners to revise existing designs, package the new bitstream programming files with theprovided software utilities, and update the remote system through the JTAG interface using theEmbedded JTAG ACE Player.
上傳時(shí)間： 2013-11-14
上傳用戶：JIMMYCB001
This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration circuitry. As a result, neither processor nor PROM needs to be fullydedicated to performing Spartan configuration.In particular, information is provided on how the idle processing time of an on-board controller can be used to loadconfiguration data from an off-board source. As a result, it is possible to upgrade a Spartan design in the field by sending thebitstream over a network.
標(biāo)簽： Spartan XAPP FPGA 098
上傳時(shí)間： 2014-08-16
上傳用戶：adada
Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.
標(biāo)簽： Virtex FPGA PCB 設(shè)計(jì)手冊(cè)
上傳時(shí)間： 2014-01-13
上傳用戶：竺羽翎2222
The exacting technological demands created byincreasing bandwidth requirements have given riseto significant advances in FPGA technology thatenable engineers to successfully incorporate highspeedI/O interfaces in their designs. One aspect ofdesign that plays an increasingly important role isthat of the FPGA package. As the interfaces get fasterand wider, choosing the right package has becomeone of the key considerations for the systemdesigner.
標(biāo)簽： Virtex 247 WP 高級(jí)封裝
上傳時(shí)間： 2013-10-22
上傳用戶：1234xhb
FPGAs have changed dramatically since Xilinx first introduced them just 15 years ago. In thepast, FPGA were primarily used for prototyping and lower volume applications; custom ASICswere used for high volume, cost sensitive designs. FPGAs had also been too expensive and tooslow for many applications, let alone for System Level Integration (SLI). Plus, the development
標(biāo)簽： Methodology Design Reuse FPGA
上傳時(shí)間： 2013-10-23
上傳用戶：旗魚旗魚
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