空時正交編碼源程序，參考文獻： V.Tarokh,H. Jafarkhani,and A. R. Calderbank "Space-Time Codes from ％Orthogonal designs",IEEE Trans. Inform. Theory VOL. 45,NO. 5,JULY 1
上傳時間： 2013-12-26
上傳用戶：fandeshun
關于FPGA流水線設計的論文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
標簽： investigates implementing pipelines circuits
上傳時間： 2015-07-26
上傳用戶：CHINA526
This was the public transportation inquiry system software engineering design documents, including the demand analysis, the outline design, the contact surface design and so on a series of designs documents, made the comprehensive analysis to the public transportation systems engineering to design ,Java,software engineering
標簽： transportation engineering documents including
上傳時間： 2015-08-15
上傳用戶：lixinxiang
This was the public transportation inquiry system software engineering design documents, including the demand analysis, the outline design, the contact surface design and so on a series of designs documents, made the comprehensive analysis to the public transportation systems engineering to design ,Java,software
標簽： transportation engineering documents including
上傳時間： 2013-12-26
上傳用戶：Zxcvbnm
This was the public transportation inquiry system software engineering design documents, including the demand analysis, the outline design, the contact surface design and so on a series of designs documents, made the comprehensive analysis to the public transportation systems engineering to design ,Java
標簽： transportation engineering documents including
上傳時間： 2015-08-15
上傳用戶：caixiaoxu26
This was the public transportation inquiry system software engineering design documents, including the demand analysis, the outline design, the contact surface design and so on a series of designs documents, made the comprehensive analysis to the public transportation systems engineering to
標簽： transportation engineering documents including
上傳時間： 2015-08-15
上傳用戶：時代電子小智
This was the public transportation inquiry system software engineering design documents, including the demand analysis, the outline design, the contact surface design and so on a series of designs documents, made the comprehensive analysis
標簽： transportation engineering documents including
上傳時間： 2014-01-07
上傳用戶：saharawalker
Triscend supports the use of the Model Technology ModelSim logic simulator for VHDL simulation of designs implemented in the Configurable System Logic (CSL) portion of a Triscend device.
標簽： Technology simulation simulator the
上傳時間： 2013-12-26
上傳用戶：zl5712176
Integration的EZMac Lite，對于開發IA4420/4421很有用！ Fixed packet length protocol MAC layer for simplifying EZRadio designs.
標簽： Integration EZMac Lite
上傳時間： 2014-01-27
上傳用戶：曹云鵬
Integration的EZMac Plus，對于開發IA4420/4421很有用！ Variable packet length protocol with packet forwarding capability MAC layer for simplifying EZRadio designs
標簽： Integration EZMac Plus
上傳時間： 2016-05-12
上傳用戶：alan-ee
