This document describes functionalities of SM VoyagerGX windows ce drivers which support wince 4.x.SM deviCE drivers are developed in c++.
標簽： functionalities describes VoyagerGX document
上傳時間： 2017-03-03
上傳用戶：qq521
Phison MP2232 based usb controller development tool. Tweakand customize other settings of MP2232 based USB Mass storage deviCE.
標簽： 2232 development controller customize
上傳時間： 2013-12-26
上傳用戶：koulian
it is a verilog code written for digital watch in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 deviCE]
標簽： synthesize simulator modelsim digital
上傳時間： 2014-01-10
上傳用戶：kernaling
it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 deviCE].you can use this code in any DSP project in which data entry is required.
標簽： synthesize simulator modelsim verilog
上傳時間： 2014-06-26
上傳用戶：zhuyibin
it is a verilog code written for traffic light controller will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 deviCE].it is a state machine based code.
標簽： controller synthesize verilog traffic
上傳時間： 2017-03-22
上傳用戶：xymbian
it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 deviCE]
標簽： synthesize verilog machine written
上傳時間： 2013-12-11
上傳用戶：yepeng139
//結構 struct fb_fix_screeninfo finfo struct fb_var_screeninfo vinfo //打開設備 fd = open["/dev/fb0", O_RDWR] if [!fd] { printf["Cannot open framebuffer deviCE.\n"] exit[1] } //取得固定信息 if [ioctl[fd, FBIOGET_FSCREENINFO, &finfo]] { printf["Error reading fixed information.\n"] exit[1] } if [ioctl[fd, FBIOGET_VSCREENINFO, &vinfo]] { printf["Error reading variable information.\n"] exit[1] }
標簽： struct fb_fix_screeninfo fb_var_screeninfo finfo
上傳時間： 2014-08-16
上傳用戶：gut1234567
The AT24C512 provides 524,288 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 65,536 words of 8 bits each. The deviCE鈥檚 cascadable feature allows up to four deviCEs to share a common two-wire bus. The deviCE is optimized for use in many industrial and commercial applications where lowpower and low-voltage operation are essential. The deviCEs are available in spacesaving 8-pin PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead Leadless Array (LAP), and 8-lead SAP packages. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.
標簽： electrically programmable provides erasable
上傳時間： 2017-04-09
上傳用戶：cc1015285075
lDocumentation for VxVorks 6.2. Migration Guide, Application API Reference, Driver API Reference, BSP developers Guide, CLI Tools Users Guide, deviCE Driver Developers Guide and more.
標簽： Reference lDocumentation Application Migration
上傳時間： 2014-01-23
上傳用戶：songyue1991
The program computes the checksum and displays the result in an output port. The program is written for Microchip PIC16F877A target deviCE
上傳時間： 2014-10-28
上傳用戶：hoperingcong
