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  • 2012TI電子設(shè)計(jì)大賽——微弱信號(hào)檢測(cè)裝置

    微弱信號(hào)檢測(cè)裝置 四川理工學(xué)院 劉鵬飛、梁天德、曾學(xué)明 摘要: 本設(shè)計(jì)以TI的Launch Pad為核心板,采用鎖相放大技術(shù)設(shè)計(jì)并制作了一套微弱信號(hào)檢測(cè)裝置,用以檢測(cè)在強(qiáng)噪聲背景下已知頻率微弱正弦波信號(hào)的幅度值,并在液晶屏上數(shù)字顯示出所測(cè)信號(hào)相應(yīng)的幅度值。實(shí)驗(yàn)結(jié)果顯示其抗干擾能力強(qiáng),測(cè)量精度高。 關(guān)鍵詞:強(qiáng)噪聲;微弱信號(hào);鎖相放大;Launch Pad Abstract: This design is based on the Launch Pad of TI core board, using a lock-in amplifier technique designed and produced a weak signal detection device, to measure the known frequency sine wave signal amplitude values of the weak in the high noise background, and shows the measured signal amplitude of the corresponding value in the liquid crystal screen. Test results showed that it has high accuracy and strong anti-jamming capability. Keywords: weak signal detection; lock-in-amplifier; Launch Pad  1、引言 隨著現(xiàn)代科學(xué)技術(shù)的發(fā)展,在科研與生產(chǎn)過程中人們?cè)絹碓叫枰獜膹?fù)雜高強(qiáng)度的噪聲中檢測(cè)出有用的微弱信號(hào),因此對(duì)微弱信號(hào)的檢測(cè)成為當(dāng)前科研的熱點(diǎn)。微弱信號(hào)并不意味著信號(hào)幅度小,而是指被噪聲淹沒的信號(hào),“微弱”也僅是相對(duì)于噪聲而言的。只有在有效抑制噪聲的條件下有選擇的放大微弱信號(hào)的幅度,才能提取出有用信號(hào)。微弱信號(hào)檢測(cè)技術(shù)的應(yīng)用相當(dāng)廣泛,在生物醫(yī)學(xué)、光學(xué)、電學(xué)、材料科學(xué)等相關(guān)領(lǐng)域顯得愈發(fā)重要。 2、方案論證 針對(duì)微弱信號(hào)的檢測(cè)的方法有很多,比如濾波法、取樣積分器、鎖相放大器等。下面就針對(duì)這幾種方法做一簡(jiǎn)要說明。 方案一:濾波法。 在大部分的檢測(cè)儀器中都要用到濾波方法對(duì)模擬信號(hào)進(jìn)行一定的處理,例如隔離直流分量,改善信號(hào)波形,防止離散化時(shí)的波形混疊,克服噪聲的不利影響,提高信噪比等。常用的噪聲濾波器有:帶通、帶阻、高通、低通等。但是濾波方法檢測(cè)信號(hào)不能用于信號(hào)頻譜與噪聲頻譜重疊的情況,有其局限性。雖然可以對(duì)濾波器的通頻帶進(jìn)行調(diào)節(jié),但其噪聲抑制能力有限,同時(shí)其準(zhǔn)確性與穩(wěn)定性將大打折扣。

    標(biāo)簽: 2012 TI 電子設(shè)計(jì)大賽 微弱信號(hào)

    上傳時(shí)間: 2013-11-04

    上傳用戶:lty6899826

  • COOLMOS全面認(rèn)識(shí)

    Recently a new technology for high voltage Power MOSFETshas been introduced – the CoolMOS™ . Based on thenew device concept of charge compensation the RDS(on) areaproduct for e.g. 600V transistors has been reduced by afactor of 5. The devices show no bipolar current contributionlike the well known tail current observed during the turn-offphase of IGBTs. CoolMOS™ virtually combines the lowswitching losses of a MOSFET with the on-state losses of anIGBT.

    標(biāo)簽: COOLMOS

    上傳時(shí)間: 2013-11-14

    上傳用戶:zhyiroy

  • 高精度I2C實(shí)時(shí)時(shí)鐘的設(shè)計(jì)

    Abstract: This application note presents an overview of the operational characteristics of accurate I²C real-time clocks (RTCs),including the DS3231, DS3231M, and DS3232. It focuses on general application guidelines that facilitate use of device resources forpower management, I²C communication circuit configurations, and I²C characteristics relative to device power-up sequences andinitializations. Additional discussions on decoupling are provided to support developing strategies for mitigating power-supply pushingof device frequency.

    標(biāo)簽: I2C 高精度 實(shí)時(shí)時(shí)鐘

    上傳時(shí)間: 2013-11-23

    上傳用戶:WMC_geophy

  • 哈達(dá)瑪變換光譜儀壓縮系統(tǒng)研究

     基于數(shù)字微鏡器件(Digital Micro-mirror device,DMD)的哈達(dá)瑪變換光譜技術(shù)是一種新型的光譜成像技術(shù),在國(guó)內(nèi)很少有專門的文獻(xiàn)介紹[1-3]。文中先介紹了本實(shí)驗(yàn)采用的哈達(dá)瑪光譜儀樣機(jī)的原理以及哈達(dá)瑪成像光譜儀優(yōu)于傳統(tǒng)模板的獨(dú)特之處,即獲得多通道高能量高信噪比的光譜數(shù)據(jù),然后描述對(duì)采集到的數(shù)據(jù)做高信噪比,高分辨率壓縮處理,最后說明此方法實(shí)時(shí)性強(qiáng)、圖像失真小、實(shí)用價(jià)值高、應(yīng)用范圍廣。

    標(biāo)簽: 哈達(dá) 變換光譜儀 壓縮系統(tǒng)

    上傳時(shí)間: 2013-11-25

    上傳用戶:eastimage

  • STM32F10xxx設(shè)備中如何得到高精度ADC

    The STM32F10xxx microcontroller family embeds up to three advanced 12-bit ADCs (depending on the device) with a conversion time down to 1 μs. A self-calibration feature is provided to enhance ADC accuracy versus environmental condition changes.

    標(biāo)簽: STM 32F F10 ADC

    上傳時(shí)間: 2014-12-23

    上傳用戶:eastimage

  • MAX2691 L2 Band GPS Low-Noise Amplifier

      The MAX2691 low-noise amplifier (LNA) is designed forGPS L2 applications. Designed in Maxim’s advancedSiGe process, the device achieves high gain andlow noise figure while maximizing the input-referred 1dBcompression point and the 3rd-order intercept point. TheMAX2691 provides a high gain of 17.5dB and sub 1dBnoise figure.

    標(biāo)簽: Amplifier Low-Noise 2691 Band

    上傳時(shí)間: 2014-12-04

    上傳用戶:zaocan888

  • 模擬cmos集成電路設(shè)計(jì)(design of analog

    模擬集成電路的設(shè)計(jì)與其說是一門技術(shù),還不如說是一門藝術(shù)。它比數(shù)字集成電路設(shè)計(jì)需要更嚴(yán)格的分析和更豐富的直覺。嚴(yán)謹(jǐn)堅(jiān)實(shí)的理論無疑是嚴(yán)格分析能力的基石,而設(shè)計(jì)者的實(shí)踐經(jīng)驗(yàn)無疑是誕生豐富直覺的源泉。這也正足初學(xué)者對(duì)學(xué)習(xí)模擬集成電路設(shè)計(jì)感到困惑并難以駕馭的根本原因。.美國(guó)加州大學(xué)洛杉機(jī)分校(UCLA)Razavi教授憑借著他在美國(guó)多所著名大學(xué)執(zhí)教多年的豐富教學(xué)經(jīng)驗(yàn)和在世界知名頂級(jí)公司(AT&T,Bell Lab,HP)卓著的研究經(jīng)歷為我們提供了這本優(yōu)秀的教材。本書自2000午出版以來得到了國(guó)內(nèi)外讀者的好評(píng)和青睞,被許多國(guó)際知名大學(xué)選為教科書。同時(shí),由于原著者在世界知名頂級(jí)公司的豐富研究經(jīng)歷,使本書也非常適合作為CMOS模擬集成電路設(shè)計(jì)或相關(guān)領(lǐng)域的研究人員和工程技術(shù)人員的參考書。... 本書介紹模擬CMOS集成電路的分析與設(shè)計(jì)。從直觀和嚴(yán)密的角度闡述了各種模擬電路的基本原理和概念,同時(shí)還闡述了在SOC中模擬電路設(shè)計(jì)遇到的新問題及電路技術(shù)的新發(fā)展。本書由淺入深,理論與實(shí)際結(jié)合,提供了大量現(xiàn)代工業(yè)中的設(shè)計(jì)實(shí)例。全書共18章。前10章介紹各種基本模塊和運(yùn)放及其頻率響應(yīng)和噪聲。第11章至第13章介紹帶隙基準(zhǔn)、開關(guān)電容電路以及電路的非線性和失配的影響,第14、15章介紹振蕩器和鎖相環(huán)。第16章至18章介紹MOS器件的高階效應(yīng)及其模型、CMOS制造工藝和混合信號(hào)電路的版圖與封裝。 1 Introduction to Analog Design 2 Basic MOS device Physics 3 Single-Stage Amplifiers 4 Differential Amplifiers 5 Passive and Active Current Mirrors 6 Frequency Response of Amplifiers 7 Noise 8 Feedback 9 Operational Amplifiers 10 Stability and Frequency Compensation 11 Bandgap References 12 Introduction to Switched-Capacitor Circuits 13 Nonlinearity and Mismatch 14 Oscillators 15 Phase-Locked Loops 16 Short-Channel Effects and device Models 17 CMOS Processing Technology 18 Layout and Packaging

    標(biāo)簽: analog design cmos of

    上傳時(shí)間: 2014-12-23

    上傳用戶:杜瑩12345

  • 多層印制板設(shè)計(jì)基本要領(lǐng)

    【摘要】本文結(jié)合作者多年的印制板設(shè)計(jì)經(jīng)驗(yàn),著重印制板的電氣性能,從印制板穩(wěn)定性、可靠性方面,來討論多層印制板設(shè)計(jì)的基本要求?!娟P(guān)鍵詞】印制電路板;表面貼裝器件;高密度互連;通孔【Key words】Printed Circuit Board;Surface Mounting device;High Density Interface;Via一.概述印制板(PCB-Printed Circuit Board)也叫印制電路板、印刷電路板。多層印制板,就是指兩層以上的印制板,它是由幾層絕緣基板上的連接導(dǎo)線和裝配焊接電子元件用的焊盤組成,既具有導(dǎo)通各層線路,又具有相互間絕緣的作用。隨著SMT(表面安裝技術(shù))的不斷發(fā)展,以及新一代SMD(表面安裝器件)的不斷推出,如QFP、QFN、CSP、BGA(特別是MBGA),使電子產(chǎn)品更加智能化、小型化,因而推動(dòng)了PCB工業(yè)技術(shù)的重大改革和進(jìn)步。自1991年IBM公司首先成功開發(fā)出高密度多層板(SLC)以來,各國(guó)各大集團(tuán)也相繼開發(fā)出各種各樣的高密度互連(HDI)微孔板。這些加工技術(shù)的迅猛發(fā)展,促使了PCB的設(shè)計(jì)已逐漸向多層、高密度布線的方向發(fā)展。多層印制板以其設(shè)計(jì)靈活、穩(wěn)定可靠的電氣性能和優(yōu)越的經(jīng)濟(jì)性能,現(xiàn)已廣泛應(yīng)用于電子產(chǎn)品的生產(chǎn)制造中。下面,作者以多年設(shè)計(jì)印制板的經(jīng)驗(yàn),著重印制板的電氣性能,結(jié)合工藝要求,從印制板穩(wěn)定性、可靠性方面,來談?wù)劧鄬又瓢逶O(shè)計(jì)的基本要領(lǐng)。

    標(biāo)簽: 多層 印制板

    上傳時(shí)間: 2013-11-19

    上傳用戶:zczc

  • pci e PCB設(shè)計(jì)規(guī)范

    This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.  

    標(biāo)簽: pci PCB 設(shè)計(jì)規(guī)范

    上傳時(shí)間: 2013-10-15

    上傳用戶:busterman

  • 基于USB HID類數(shù)據(jù)通信的直流電源監(jiān)控設(shè)計(jì)

    為了實(shí)現(xiàn)直流電源的監(jiān)控,提出了一種具有USB HID數(shù)據(jù)通信功能的直流電源設(shè)計(jì)方案。詳細(xì)論述了基于STM32 USB固件庫(kù)(USB-FS device library V3.3)的自定義HID類下位機(jī)的實(shí)現(xiàn),介紹了如何在VC2010集成開發(fā)環(huán)境中編寫多線程上位機(jī)程序并運(yùn)用PlotLab(一個(gè)快速信號(hào)繪圖和可視化的VCL組件)顯示實(shí)時(shí)波形,最后再以實(shí)驗(yàn)開發(fā)板和PC實(shí)現(xiàn)了HID數(shù)據(jù)通信,證明了此監(jiān)控設(shè)計(jì)方案的可行性。

    標(biāo)簽: USB HID 數(shù)據(jù)通信 直流電源

    上傳時(shí)間: 2013-10-17

    上傳用戶:13162218709

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