All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
上傳時間： 2013-10-23
上傳用戶：copu
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
上傳時間： 2014-04-02
上傳用戶：han_zh
Abstract: This application note explains the hardware of different types of 1-Wire® interfaces and software examples adapted to this hardware with a focus on serial ports. Depending on the types of iButtons required for a project and the type of computer to be used, the most economical interface is easily found. The hardware examples shown are basically two different types: 5V general interface and 12V RS-232 interface. Within the 5V group a common printed circuit board could be used for all circuits described. The variations can be achieved by different populations of components. The same principal is used for the 12V RS-232 interface. The population determines if it is a Read all or a Read/Write all type of interface. There are other possible circuit implementations to create a 1-Wire interface. The circuits described in this application note cover many different configurations. For a custom application, one of the described options can be adapted to meet individual needs.
標簽： iButtons Reading Writing and
上傳時間： 2013-10-29
上傳用戶：long14578
I2C interface, is a very powerful tool for system designers. Theintegrated protocols allow systems to be completely software defined.Software development time of different products can be reduced byassembling a library of reusable software modules. In addition, themultimaster capability allows rapid testing and alignment ofend-products via external connections to an assembly-line computer.The mask programmable 87LPC76X and its EPROM version, the87LPC76X, can operate as a master or a slave device on the I2Csmall area network. In addition to the efficient interface to thededicated function ICs in the I2C family, the on-board interfacefacilities I/O and RAM expansion, access to EEPROM andprocessor-to-processor communications.
標簽： microcontro Using 76X LPC
上傳時間： 2013-12-30
上傳用戶：Artemis
為了擴大監控范圍，提高資源利用率，降低系統成本，提出了一種多通道視頻切換的解決方案。首先從視頻信號分離出行場信號，然后根據行場信號由DSP和FPGA產生控制信號，控制多路視頻通道之間的切換，從而實現讓一個視頻處理器同時監控不同場景。實驗結果表明，該方案可以在視頻監控告警系統中穩定、可靠地實現視頻通道的切換。 Abstract: To expand the scope of monitoring， improve resource utilization， reduce system cost， a multiple video channels signal switching method is pointed out in this paper. First， horizontal sync signal and field sync signal from the video signal are separated， then control signal according to the sync signal by DSP and FPGA is generated to control the switching between multiple video channels. Thus， it achieves to make a video processor to monitor different place. Experimental results show that the method can realize video channel switching reliably， and is applied in the video monitoring warning system successfully.
上傳時間： 2013-11-09
上傳用戶：不懂夜的黑
Field Programmable Gate Arrays (FPGAs) are becoming a critical part of every system design. Many vendors offer many different architectures and processes. Which one is right for your design? How do you design one of these so that it works correctly and functions as you expect in your entire system? These are the questions that this paper sets out to answer.
上傳時間： 2013-10-29
上傳用戶：lixqiang
In today’s world of modular networking and telecommunications design, it is becomingincreasingly difficult to keep alignment with the many different and often changing interfaces,both inter-board and intra-board. Each manufacturer has their own spin on the way in whichdevices are connected. To satisfy the needs of our customers, we must be able to support alltheir interface requirements. For us to be able to make products for many customers, we mustadopt a modular approach to the design. This modularity is the one issue that drives the majorproblem of shifting our bits from one modular interface to another.
上傳時間： 2013-11-25
上傳用戶：suicone
為滿足無線網絡技術具有低功耗、節點體積小、網絡容量大、網絡傳輸可靠等技術要求，設計了一種以MSP430單片機和CC2420射頻收發器組成的無線傳感節點。通過分析其節點組成，提出了ZigBee技術中的幾種網絡拓撲形式，并研究了ZigBee路由算法。針對不同的傳輸要求形式選用不同的網絡拓撲形式可以盡大可能地減少系統成本。同時針對不同網絡選用正確的ZigBee路由算法有效地減少了網絡能量消耗，提高了系統的可靠性。應用試驗表明，采用ZigBee方式通信可以提高傳輸速率且覆蓋范圍大，與傳統的有線通信方式相比可以節約40%左右的成本。 Abstract: To improve the proposed technical requirements such as low-ower， small nodes， large capacity and reliable network transmission， wireless sensor nodes based on MSP430 MCU and CC2420 RF transceiver were designed. This paper provided network topology of ZigBee technology by analysing the component of the nodes and researched ZigBee routing algorithm. Aiming at different requirements of transmission mode to choose the different network topologies form can most likely reduce the system cost. And aiming at different network to choose the correct ZigBee routing algorithm can effectively reduced the network energy consumption and improved the reliability of the system. Results show that the communication which used ZigBee mode can improve the transmission rate， cover more area and reduce 40% cost compared with traditional wired communications mode.
上傳時間： 2013-10-09
上傳用戶：robter
superpro 3000u 驅動 PIC16C65B@QFP44 [SA245] PIC16C65B: Part number QFP44: Package in QFP44 SA245: Adapter purchase number AM29DL320GT@FBGA48 [SA642+B026] AM29DL320GT: Part number FBGA48: Package in FBGA48 SA642: Adapter purchase number (Top board with socket) B026: Adapter purchase number (Bottom board, exchangable for different parts) 87C196CA@PLCC68(universal adapter) [PEP+S414T] 87C196CA: Part number PLCC68: Package in PLCC68 universal adapter: this adapter is valid for all parts in this package PEP: The PEP (Pin-driver Expansion Pack necessary to work with the adapter S414T) S414T: Adapter purchase number (Universal for all parts in this package) S71PL127J80B@FBGA64(special adapter) [(SA642A-B079A-Y096AF001)] S71PL127J80B: Part number FBGA64: Package in FBGA64 special adapter: this adapter is valid for this
上傳時間： 2013-10-23
上傳用戶：Avoid98
Today’s digital systems combine a myriad of chips with different voltage configurations.Designers must interface 2.5V processors with 3.3V memories—both RAM and ROM—as wellas 5V buses and multiple peripheral chips. Each chip has specific power supply needs. CPLDsare ideal for handling the multi-voltage interfacing, but do require forethought to ensure correctoperation.
上傳時間： 2013-11-10
上傳用戶：yy_cn
