LTE-Advanced becomes a truly global standard for 4G cellular communications. Relay, as one of the key technologies of LTE-Advanced, can significantly extend the coverage, and improve the system throughput. LTE-A standards and tech- nologies were described in several recent books where the limited pages for relay feature prevent the detailed explanations of the technology. In this book, we tried to provide an in-depth description of LTE-A relay development. More specifically, significant portions are spent on relay channel modeling and potential technologies during the study item phase of the development, although some of those tech- nologies, such as Type 2 cooperative relay, multi-hop relay, relay with backhaul of carrier aggregation, were not standardized in Release 10 LTE.
標簽： LTE-Advanced Technology Relay
上傳時間： 2020-05-27
上傳用戶：shancjb
Mobile operators must continuously pursue cost‐ effective and efficient solutions to meet the high data demand requirements of their subscribers. Limited spectrum allocations and non‐contiguous spectrum blocks continue to pose challenges for mobile operators supporting large data uploads and downloads across their networks. With the increase in video and social media content, the challenges have increased exponentially.
標簽： qorvo-carrier-aggregation-fundame ntals
上傳時間： 2020-05-31
上傳用戶：shancjb
關(guān)于FPGA流水線設(shè)計的論文\r\nThis work investigates the use of very deep pipelines for\r\nimplementing circuits in FPGAs, where each pipeline\r\nstage is limited to a single FPGA logic element (LE). The\r\narchitecture and VHDL design of a parameterized integer\r\na
上傳時間： 2013-09-03
上傳用戶：wl9454
Abstract: There are many things to consider when designing a power supply for a field-programmablegate array (FPGA). These include (but are not limited to) the high number of voltage rails, and thediffering requirements for both sequencing/tracking and the voltage ripple limits. This application noteexplains these and other power-supply considerations that an engineer must think through whendesigning a power supply for an FPGA.
上傳時間： 2013-11-12
上傳用戶：金苑科技
Abstract: Some types of loads require more current during startup than when running. Other loads can be limited to a lower-powercurrent during startup but require a higher operating current. This article describes an application circuit that automatically adjusts apower circuit’s overcurrent protection level up or down after startup is complete.
標簽： FET 保護 集成 電源開關(guān)
上傳時間： 2013-10-23
上傳用戶：swaylong
For a variety of reasons, it is desirable to charge batteriesas rapidly as possible. At the same time, overchargingmust be limited to prolong battery life. Such limitation ofovercharging depends on factors such as the choice ofcharge termination technique and the use of multi-rate/multi-stage charging schemes. The majority of batterycharger ICs available today lock the user into one fixedcharging regimen, with at best a limited number ofcustomization options to suit a variety of application needsor battery types. The LTC®1325 addresses these shortcomingsby providing the user with all the functionalblocks needed to implement a simple but highly flexiblebattery charger (see Figure 1) which not only addressesthe issue of charging batteries but also those of batteryconditioning and capacity monitoring.
上傳時間： 2013-10-19
上傳用戶：royzhangsz
The design of battery-powered equipment can often bequite challenging. Since few ICs can operate directly fromthe end-of-life voltage from a 2-cell battery (about 1.8V),most systems require a DC/DCconverter. The systemdesigner often has a limited area in which to place the DC/DC converter; associated inductors and capacitors must be
上傳時間： 2013-11-23
上傳用戶：wys0120
在理論分析循環(huán)碼編碼和譯碼基本原理的基礎(chǔ)上，提出了基于單片機系統(tǒng)的(24，16)循環(huán)碼軟件實現(xiàn)編碼、譯碼的方案。仿真結(jié)果表明(24，16)循環(huán)碼能有效地克服來自通訊信道的干擾，保證數(shù)據(jù)通信的可靠及系統(tǒng)的穩(wěn)定，使誤碼率大幅度降低。本論文對(24，16)循環(huán)碼的研究結(jié)果表明，可以有效地降低錯誤概率和提高系統(tǒng)的吞吐量，實現(xiàn)糾錯僅需要在接收端增加有限的存儲空間和計算復(fù)雜度，具有一定的實用價值。 Abstract: Based on analyzing the theory of encoding and decoding of cyclic code， this paper showed the schemes of encoding and decoding of(24，16)cyclic code by the software and based on microcontroller. Simulation results show that using (24，16) cyclic codes can effectively overcome the interference from communication channel， ensure the reliability and stability of data communication systems， and reduce the bit error rate greatly. The results of this paper show that by using the (24，16) cyclic code， the error rate can be reduced and the system throughput can be improved. Meanwhile， the system only needs to enlarge limited storage space and computation the complexity at the receiving end to realize error correction. Thus the (24，16) cyclic code has a practical value.
標簽： 24 16 單片機系統(tǒng) 循環(huán)碼
上傳時間： 2013-11-09
上傳用戶：gaoliangncepu
單片機作為一種微型計算機，其內(nèi)部具有一定的存儲單元（8031除外），但由于其內(nèi)部存儲單元及端口有限，很多情況下難以滿足實際需求。為此介紹一種新的擴展方法，將數(shù)據(jù)線與地址線合并使用，通過軟件控制的方法實現(xiàn)數(shù)據(jù)線與地址線功能的分時轉(zhuǎn)換，數(shù)據(jù)線不僅用于傳送數(shù)據(jù)信號，還可作為地址線、控制線，用于傳送地址信號和控制信號，從而實現(xiàn)單片機與存儲器件的有效連接。以單片機片外256KB數(shù)據(jù)存儲空間的擴展為例，通過該擴展方法，僅用10個I/O端口便可實現(xiàn)，與傳統(tǒng)的擴展方法相比，可節(jié)約8個I/O端口。 Abstract: As a micro-computer,the SCM internal memory has a certain units(except8031),but because of its internal storage units and the ports are limited,in many cases it can not meet the actual demand.So we introduced a new extension method,the data line and address lines combined through software-controlled approach to realize the time-conversion functions of data lines and address lines,so the data lines not only transmited data signals,but also served as address lines and control lines to transmit address signals and control signals,in order to achieve an effective connection of microcontroller and memory chips.Take microcontroller chip with256KB of data storage space expansion as example,through this extension method,with only10I/O ports it was achieved,compared with the traditional extension methods,this method saves8I/O ports.
標簽： 單片機 P0口 數(shù)據(jù)存儲器 擴展
上傳時間： 2014-12-26
上傳用戶：adada
The MSP-FET430PIF is a Parallel Port interface (does not include target board) that is used to program and debug MSP430 FET tools and test boards through the JTAG interface. This interface is included in our FET tools, but sold without the development board. This interface uses a Parallel PC Port to communicate to the Debugger Software (IAR Kickstart software included) running on the PC. The interface uses the standard 14 pin header to communicate to the MSP430 device using the standard JTAG protocol. The flash memory can be erased and programmed in seconds with only a few keystrokes, and since the MSP430 flash is extremely low power, no external power supply is required. The tool has an integrated software environment and connects directly to the PC which greatly simplifies the set-up and use of the tool. The flash development tool supports development with all MSP430 flash parts. Features MSP430 debugging interface to connect a MSP430-Flash-device to a Parallel port on a PC Supports JTAG debug protocol (NO support for Spy-Bi-Wire (2-wire JTAG) debug protocol, Spy-Bi-Wire (2-wire JTAG) is supported by MSP-FET430UIF) Parallel Port cable and a 14-conductor target cable Full documentation on CD ROM Integrated IAR Kickstart user interface which includes: Assembler Linker Limulator Source-level debugger Limited C-compiler Technical specifications: Backwardly compatable with existing FET tool boards.
上傳時間： 2013-10-26
上傳用戶：fengweihao158@163.com
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