1.an fpga implementation of the image space reconstruction algorithm for hyperspectral imaging analysis\r\n2. fpga implemention of a median filter\r\n3. fpga implementation of digital filters\r\n4.hardware acceleration of edge detection algorithm on fpgas
標簽： implementation reconstruction hyperspectral algorithm
上傳時間： 2013-08-07
上傳用戶：ytulpx
模擬和數字電子電路基礎
標簽： Foundations Electronic Circuits Agarwal
上傳時間： 2013-11-15
上傳用戶：fdfadfs
為了滿足現代高速通信中頻率快速轉換的需求，基于坐標旋轉數字計算（CORDIC，Coordinate Rotation digital Computer）算法完成正交直接數字頻率合成（ODDFS，Orthogonal Direct digital Frequency Synthesizer）電路設計方案。采用MATLAB和Xilinx System Generator開發工具搭建電路的系統模型，通過現場可編程門陣列（FPGA，Field Programmable Gate Array）完成電路的寄存器傳輸級（RTL，Register Transfer Level）驗證，仿真結果表明電路設計具有很高的有效性和可行性。
上傳時間： 2013-11-09
上傳用戶：hfnishi
Abstract: Many digital devices incorporate analog circuits. For instance, microprocessors, applicationspecificintegrated circuits (ASICs), and field-programmable gate arrays (FPGAs) may have internalvoltage references, analog-to-digital converters (ADCs) or digital-to-analog converters (DACs). However,there are challenges when you integrate more analog onto a digital design. As with all things in life, inelectronics we must always trade one parameter for another, with the application dictating the propertrade-off of analog function. In this application note, we examine how the demand for economy of spaceand cost pushes analog circuits onto digital substrates, and what design challenges emerge.
上傳時間： 2013-11-17
上傳用戶：菁菁聆聽
Abstract: This application note describes a new generation of digital-input Class D audio amplifiers that achieve high PSRRperformance, comparable to traditional analog Class D amplifiers. More importantly, these digital-input Class D amplifiersprovide additional benefits of reduced power, complexity, noise, and system cost.
上傳時間： 2013-12-20
上傳用戶：JIUSHICHEN
Abstract: This application note describes how sampling clock jitter (time interval error or "TIE jitter") affectsthe performance of delta-sigma digital-to-analog converters (DACs). New insights explain the importanceof separately specifying low-frequency (< 2x passband frequency) and high-frequency or wideband (> 2xpassband frequency) jitter tolerance in these devices. The article also provides an application example ofa simple highly jittered cycle-skipped sampling clock and describes a method for generating a properbroadband jittered clock. The document then goes on to compare Maxim's audio DAC jitter tolerance tocompetitor audio DACs. Maxim's exceptionally high jitter tolerance allows very simple and low-cost sampleclock implementations.
上傳時間： 2013-10-25
上傳用戶：banyou
Abstract: A digital RF modulator, an integrated solution that satisfies stringent DOCSIS RF-performancerequirements, takes advantage of modern technologies like high-performance wideband digital-to-analogconversion and CMOS technology scaling. This application note describes the concept and advantages ofa digital quadrature amplitude modulation (QAM) modulator that uses the direct-RF architecture to enablea cable access platform (CCAP) system.
上傳時間： 2013-10-20
上傳用戶：drink！
The MAX5713/MAX5714/MAX5715 4-channel, low-power,8-/10-/12-bit, voltage-output digital-to-analog converters(DACs) include output buffers and an internal referencethat is selectable to be 2.048V, 2.500V, or 4.096V. TheMAX5713/MAX5714/MAX5715 accept a wide supplyvoltage range of 2.7V to 5.5V with extremely low power(3mW) consumption to accommodate most low-voltageapplications. A precision external reference input allowsrail-to-rail operation and presents a 100kI (typ) load toan external reference.
上傳時間： 2013-12-23
上傳用戶：ArmKing88
Abstract: This design idea explains how to implement an 8-bit analog-to-digital converter (ADC), using a microcontroller
上傳時間： 2013-10-30
上傳用戶：愛死愛死
Abstract: The DS4830 optical microcontroller's analog-to-digital converter (ADC) offset can change with temperature and gainselection. However, the DS4830 allows users to measure the ADC internal offset. The measured ADC offset is added to the ADCoffset register to nullify the offset error. This application note demonstrates the DS4830's ADC internal offset calibration in theapplication program.
上傳時間： 2014-12-23
上傳用戶：萍水相逢
