The STWD100 watchdog timer circuits are self-contained devices which prevent systemfailures that are caused by certain types of hardware errors (non-responding peripherals,bus contention, etc.) or software errors (bad code jump, code stuck in loop, etc.).The STWD100 watchdog timer has an input, WDI, and an output, WDO (see Figure 2). Theinput is used to clear the internal watchdog timer periodically within the specified timeoutperiod, twd (see Section 3: Watchdog timing). While the system is operating correctly, itperiodically toggles the watchdog input, WDI. If the system fails, the watchdog timer is notreset, a system alert is generated and the watchdog output, WDO, is asserted (seeSection 3: Watchdog timing).The STWD100 circuit also has an enable pin, EN (see Figure 2), which can enable ordisable the watchdog functionality. The EN pin is connected to the internal pull-downresistor. The device is enabled if the EN pin is left floating.
IrCOMM2k - Virtual Infrared COM Port for Windows 2000/XP。
2. FILES IN THIS ARCHIVE:
- Setup.exe (setup and uninstall program)
- ircomm2k.exe (service program)
- ircomm2k.sys (device driver)
- ircomm2k.dll (device property page)
- ircomm2k.hlp (property page context help)
- ircomm2k.inf (setup script for windows)
- Readme.txt (this file)
- License.txt (terms of license)
3. INSTALLATION
1. unzip IrCOMM2k-1.2.0.zip in a new folder
2. run the setup program
3. disable the image transfer under wireless link
SAM9261 BasicMMU Example code with ADS1.2 (163 kB) The goal of this project is to show how to use a PC100 SDRAM and the MMU to perform a rating with a 100MHz Bus Clock. The rating is based on Dhrystone 2.1. It shows the rate when I+D Caches are disabled or enabled, with or without MMU and I Cache is disable or enabled, with or without MMU.
NRF905驅動代碼
// The content of this struct is nRF905 s initialize data.
// CH_NO=1 433MHZ Normal Opration,No Retrans RX,TX Address is 4 Bytes
// RX TX Payload Width is 32 Bytes disable Extern Clock Fosc=16MHZ
// 8 Bits CRC And enable
